I have been at odds trying to make +uvm_set_config_int to work for a member declared in a uvm_object.
class enc_sel_example extends uvm_object;
rand bit m_enc_sel;
uvm_object_utils_begin(enc_sel_example)
uvm_field_int(m_enc_sel, UVM_DEFAULT)
`uvm_object_utils_endconstraint c_enc_sel {
this.m_enc_sel inside {[0:1]};
}
//------------------------------------------------------------------------------
// post_randomize function
//------------------------------------------------------------------------------
function void post_randomize();
super.post_randomize();
uvm_config_db#(uvm_bitstream_t)::get(null, “”, “m_enc_sel”, m_enc_sel); > endfunction : post_randomize
endclass : enc_sel_example
sim_cmd +uvm_set_config_int=“*,m_enc_sel,0”
The above does not work. I have seen posts where it is said that these uvm plus args only work for uvm_components. Is that the reason I am not able to use