Accessing complex hierarchy through bind statement

SystemVerilog
1

Hi,

I have a module dut which instantiates another module sec_dut.
I want to access the signals inside sec_dut from the coverage module cv using bind.

I can access them one by one like below but it is parameterized, so this won’t solve the problem.

bind (
…
.y1c(dut_s[1].sdut.y1),
…
);

What will be the best way to access this hierarchy in this case.

Thanks.

edaplayground link: EDA Playground

2

You can create an array of wires and connect each element with another generate statement.

module cv #(int n)(
  input [2:0] ac,
  input [2:0] bc,
  input [4:0] zc,
  input [2:0] y1c[n],
  input clkc,
  input rst_nc
);

  initial begin
    #50; foreach(y1c[i]) 
      $display("CV[%0d]: %0d", i,y1c[i]);
  end
    
endmodule

module tb;
  
  bit clk;
  bit rst_n;
  
  bit [2:0] a0, b0;
  bit [4:0] z;
  parameter N = 4;
  dut #(.pj(N)) d1 (
    .*
  );
  
  initial forever #5 clk = ~clk;
  
  initial begin
    @(negedge clk) rst_n = 1; a0 = 3; b0 = 3;
    #100 $finish;
  end
  
  logic [2:0] y1[N];

  for (genvar i=0; i<N; i++) assign y1[i] = d1.dut_s[i].sdut.y1;

  
  bind dut cv #(pj) cv1(
    .ac(a0),
    .bc(b0),
    .zc(z),
    .y1c(tb.y1),
    .clkc(clk),
    .rst_nc(rst_n)
  );
  
endmodule
3

Thanks Dave. Got it!