Verification Academy

Topic	Replies	Views	Activity
Two Clock in Clocking block UVM UVM , Clocking-Block	13	740	June 27, 2023
Problems with uvm_config_db#()::get() in a class called tinyalu_agent_cfg UVM UVM	9	283	October 9, 2023
Dynamic type casting Error UVM UVM , cast , dynamic-typecas	9	320	August 9, 2023
SV Proability Constraint for Number of Set Bits SystemVerilog	4	335	January 16, 2024
UVM Verification project ideas UVM	3	257	February 25, 2024
Assertion to check for signal propagation SystemVerilog assertion	8	395	January 15, 2024
Constraint Interview Question SystemVerilog constraint-randomization	7	517	January 23, 2024
Constraint Question : Write a constraint for 2D Array where value of an element should be different from its neighbor SystemVerilog constraint-randomization	5	396	January 15, 2024
Constraint to Generate 10 bit number with set bits such that no set bits are together SystemVerilog constraint-randomization	7	284	February 17, 2024
Interview question on assertion Downloads Downloads	0	391	July 8, 2023
Coverpoint for dist Coverage SystemVerilog , Coverage , System-Verilog	1	251	January 2, 2024
How we can use task as function and function as task? SystemVerilog	1	63	April 3, 2024
Interview Question on UVM UVM	4	110	April 8, 2024
3 unique arrays - constraint SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	1	107	April 3, 2024
2D Array Column Sum Constraint Failing SystemVerilog constraint-randomization , systemverilog-constraint	3	336	January 16, 2024
Constraint for walking pattern (walking 1's) SystemVerilog systemverilog-constraint , uvm-sv-constraints	7	140	April 19, 2024
N Queen Board Problem in SV Constraint SystemVerilog SystemVerilog , systemverilog-constraint , array-reducation , Constraint-Interview-Question	7	613	April 23, 2024
Constraint to Generate Deck of 52 Cards SystemVerilog constraint-randomization , Constraint-Interview-Question	4	324	January 23, 2024
What is the advantage or the main purpose of using Followed by operator in SVA? SystemVerilog assertion , operators , SVA-Assertion-Systemverilog	4	192	January 14, 2024
DUT reference model location? UVM SystemVerilog , UVM	2	74	April 7, 2024
Expression coverage Coverage Coverage	4	193	February 21, 2024
SV Constraint :: Address must be aligned to the size of the transfer SystemVerilog SystemVerilog , constraint , constraint-randomization	7	192	March 14, 2024
What is the difference between using #10 and ##10 inside initial block? SystemVerilog SystemVerilog , delays	2	216	January 16, 2024
SV Constraint Question SystemVerilog SystemVerilog , constraint-randomization	1	497	July 7, 2023
Systemverilog constraints SystemVerilog constraint-randomization , systemverilog-constraint	5	346	January 16, 2024
Using std::randomize SystemVerilog SystemVerilog , constraint-randomization	4	175	February 14, 2024
How to call the C testcase, for SOC verification UVM UVM	6	450	January 6, 2024
Race condition of delay statement inside procedural code SystemVerilog	1	215	January 16, 2024
There are 2 agents. can Monitor from agent A communicate with Sequencer of Agent B. If yes how? UVM UVM , testbench	3	169	February 28, 2024
Constraints failure SystemVerilog constraint-randomization	2	65	March 29, 2024
How to kill fork join if some of the threads ae finished SystemVerilog	1	60	April 25, 2024
Inheritance of clock for sequence used as event control SystemVerilog SystemVerilog , System-Verilog , SVA	4	190	January 16, 2024
Waveform for this assertion SystemVerilog SystemVerilog	5	327	December 20, 2023
What are some examples of protocol checking in monitor? UVM	3	236	January 16, 2024
Divide an array into two arrays SystemVerilog	6	321	January 9, 2024
Regarding const'() cast SystemVerilog SystemVerilog , Regarding-const-cast	5	416	January 10, 2024
Is there any way to set a global solve...before? SystemVerilog SystemVerilog , constraint , solve-before	1	77	April 3, 2024
How to abort from execution of an asynchronous timeout property? SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	3	175	January 15, 2024
Scoreboard for 2x2 router UVM	5	110	April 2, 2024
How to write a checker for this kind of DUT SystemVerilog	5	167	January 10, 2024
SVA assertion to check condition is satisfied until one signal asserted SystemVerilog	8	162	February 13, 2024
Solve before constraint used with implication operator SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	7	92	April 6, 2024
Raise_objection/ drop_obejction UVM UVM	2	125	February 13, 2024
Constraint for 4 Queens Problem SystemVerilog	3	108	April 12, 2024
Using property expression ( a[0] ##1 b[0] ) \|=> c SystemVerilog SystemVerilog , assertion , SVA	5	237	January 3, 2024
SV Interfaces: best coding style to encapsulate functionality? SystemVerilog SystemVerilog , Interfaces	8	1025	October 12, 2023
How to get(access) the data members(properties) of sequencer from driver? UVM UVM	6	124	January 10, 2024
Regarding UVM Factory Macros UVM	4	173	January 17, 2024
Uvm_config_db get in UVM_object UVM UVM , UVM-Configuration-database , UVMconfiguration	8	792	May 18, 2023
Use of an Associative array or Queue in System Verilog Assertion Property SystemVerilog SystemVerilog , UVM , assertion , System-Verilog , queue , property , accessing-the-associative-array-elements	6	162	February 23, 2024