Verification Academy

Topic	Replies	Views	Activity
Write an SVA - if signal b rose high then in the past {x:y] cycle signal a should be high . I am only aware of $past which checks at a particular cycle in the past , how to take care in case we need to check for few cycles in the past SystemVerilog assertion	2	269	May 15, 2025
Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts UVM UVM	1	190	July 2, 2025
Assertions in UVM SystemVerilog assertion	4	135	August 26, 2025
Randomization and control SystemVerilog	4	120	August 3, 2025
Functional Coverage At Subsystem or SOC Level SystemVerilog UVM , code-coverage , SystemVerilog-FunctionalCoverage	2	185	June 10, 2025
Sample level triggered signal Coverage Coverage	6	143	June 25, 2025
Best approach to achieve prime number via constraint SystemVerilog constraint-randomization , randomization , prime-number-constraint	4	183	October 2, 2025
Constraint Solver error SystemVerilog	5	120	May 27, 2025
Power aware verification UVM Low-Power--UPF	1	210	April 14, 2025
System verilog assertion UVM	2	102	July 28, 2025
Randomization of req signal in priority arbiter SystemVerilog constraint-randomization , Priority-arbiter	7	105	March 10, 2026
Uvm_phase : build_phase UVM UVM	6	150	June 12, 2025
Reset code in uvm UVM UVM , reset	3	229	May 12, 2025
Question on use of RAL model for System-On-Chip verification UVM	4	165	October 24, 2025
Write function not getting executed in monitor UVM	5	106	September 11, 2025
Timescale versus UVM info? UVM UVM , realtime , Timescale	5	141	March 29, 2025
Transaction-Level Testbenches for FPGA Simulation SystemVerilog OVM , UVM	2	216	April 30, 2025
Wait for variable cycles number before triggering property SystemVerilog assertion	3	120	July 18, 2025
Regarding disable iff SystemVerilog assertion , SVA , property , Dave-Rich , disable-iff , Ben-Cohen	3	175	June 20, 2025
Synchronization of transactions parallel incoming in UVM scoreboard UVM SystemVerilog , UVM , data-flow-synchronization , Synchronization	3	134	May 6, 2025
How to have RAL write to DUT without predicting UVM RAL	4	109	August 4, 2025
System verilog Assertion SystemVerilog assertion	4	120	January 1, 2026
How to use uvm_mem? UVM UVM	4	195	April 4, 2025
Type cast error for uvm config db UVM	6	103	June 29, 2025
Using ternary operator as an alternative to if-else in consequent SystemVerilog assertion , SVA	3	118	August 5, 2025
Running sequences through start_item UVM	3	177	April 18, 2025
Streaming operator SystemVerilog	7	278	March 28, 2025
VIP based verification UVM	2	130	November 27, 2025
What is an interface? not in code but inside a chip what is it actually? what does it contain? Im confusing it with protocol SystemVerilog	1	67	May 21, 2025
Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other SystemVerilog constraint-randomization , 2Darray	4	125	January 5, 2026
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	121	October 27, 2025
Assertion on gated clock and after some time ungated clock SystemVerilog assertion , System-Verilog , SVA , Assertion-system-verilog , Assertion-property	3	158	April 10, 2025
How to set_inst_override_by_type a uvm_reg UVM	7	112	December 4, 2025
Randomization results for signed variables and assignment to RAL variable SystemVerilog SystemVerilog	7	100	April 10, 2025
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	4	233	March 27, 2025
Constraint to generate pattern SystemVerilog SystemVerilog	4	157	March 25, 2025
Constraint to make sure each value gets randomized at least once SystemVerilog	4	162	March 13, 2025
UVM FACTORY Example Usage UVM uvm-factory , uvm-factory-override	2	126	December 18, 2025
Uvm_scoreboard run_phase wrt queue logic UVM Queues , UVM-scoreboard	3	150	June 2, 2025
Assertion for 55mhz clock SystemVerilog	3	141	May 22, 2025
Invoking response_handler even after seq_h.start completes UVM Response-Handler	4	133	August 8, 2025
What is False Coverage and hole in coverage ? How to solve them? Coverage SystemVerilog , Coverage	1	263	April 2, 2025
Calling a Task at the end of run_phase UVM UVM , UVM-phases	3	96	January 17, 2026
Verifying synchronours fifo SystemVerilog	3	112	November 11, 2025
Transactions from ref_model not arriving at scoreboard UVM	3	116	May 16, 2025
Configuring agent in Active / Passive mode UVM uvm_config_db , activepassive-agent-configuration , uvm_agent , uvm_active_passive_enum	5	123	February 22, 2026
SVA assertions and preponed region evaluation SystemVerilog	5	258	May 20, 2025
Illegal assignment mailbox error SystemVerilog	6	95	July 2, 2025
Clock Frequency Verification SystemVerilog	1	114	July 10, 2025
Why we are not raising and dropping objection in driver run_phase? UVM UVM	1	217	March 30, 2025