Inheritance of clock for sequence used as event control

SystemVerilog
, ,
1

Hi All,
Consider the following code ::

 default clocking cb @(posedge clk); endclocking

  sequence  sr1;
     req ##2 gnt ;  // No explicit clocking event
  endsequence

  always @( sr1 )  
    $display(" TIME : %3t  Sequence  sr1  completes " , $time)

On trying this on 2023 version of licensed tools I observe ::
2 tools treat the code legal i.e sr1 inherits the clock from default clocking block whereas
1 tools throws a compilation error : “Use of a method on an unclocked sequence is illegal.”

[Q] Does the LRM say that the default clock will be inherited by the sequence sr1 ?
If yes,could you please point to the respective LRM section ?

2

14.12 Default clocking
One clocking block can be specified as the default for all cycle delay operations within a given module,
interface, program, or checker.

So I would argue that the compile error needs a fix in the tool.

3

So I would argue that the compile error needs a fix in the tool.

Thanks Srini.
I am looking at LRM 16.16 Clock resolution ::

In a module, interface, program, or checker with a default clocking event, a concurrent assertion
statement that has no otherwise specified leading clocking event is treated as though the default
clocking event had been written explicitly as the leading clocking event.

I believe the above quote is applicable as well.

1 Like
4

Yes, for any concurrent SVA in that module. In your test code, you didn’t show one though.

5

My apologies Srini. I was testing the code within a module.