How to write a checker for this kind of DUT

SystemVerilog
1

Hi There,

what are the ways to write a checker for write-only DUTs?

thanks & regards,
Teja.

2

You can include a checker in the dut, or you can bind a verification module to the dut.
Ben

3

No, my question is if the DUT has capabilities like reading and writing then we can write and read data and verify whether the DUT is working properly or not( by having a reference model in the scoreboard). In my case, DUT has only writing capability in this case what will be my checker how can I verify my data.

Thanks & Regards,
Teja.

4

Even it has the read capability, you might still don’t want to verify it by doing something like WR+RD and compare. This probably doesn’t reveal any unwanted memory aliasing problem. Frontdoor write + backdoor check seems to be better.

5

Look at your verification goals/plan. That should give you an idea of what to verify. Below are some generic thoughts:

  1. Write protocol (such wr-en goes high, addr/data not unknown)
  2. Write timing across signals
  3. How does the DUT indicate that WR is successful?
  4. Maybe you can use backdoor to access the target write location and cross check in SBRD

HTH

6

Very curious requirement and application for a DUT that can only write and has no read or output capabilities!
It is like a bridge to nowhere. Actually, it reminds me of the Winchester Mystery House

Winchester Mystery House: Cheat Sheetwas built by Sarah Winchester from 1884 until her death in 1922. The house is a labyrinth of approximately 160 rooms and bizarre features such as stairs that lead nowhere, doors that open onto walls, columns that are installed upside down and chimneys that don’t reach the ceiling
winchester