3 unique arrays - constraint

SystemVerilog
, ,
1

Hey Everyone,

I have constraints below for three arrays to be unique (unique from each other as well). This works as expected.

Wondering if there is a more efficient way to do this. Thanks.

class Main;
  rand bit[11:0] arr1[5], arr2[5], arr3[5];
  
  
  constraint c0{unique {arr1, arr2, arr3};}
       
  constraint c1 {foreach(arr1[i]){
    !(arr1[i] inside arr2);
  }};
  constraint c2 {foreach(arr1[i]){
    !(arr1[i] inside arr3);
  }};
  constraint c3 {foreach(arr3[i]){
    !(arr3[i] inside arr1);
  }};
  constraint c4 {foreach(arr3[i]){
    !(arr3[i] inside arr2);
  }};
  
  constraint c5 {foreach(arr2[i]){
    !(arr2[i] inside arr1);
  }};
  constraint c6 {foreach(arr2[i]){
    !(arr2[i] inside arr3);
  }};
endclass

module TB;
  Main M;

  initial begin
    M = new();
    assert(M.randomize());
    $display("arr1 = %p, arr2 = %p, arr3 = %p", M.arr1, M.arr2, M.arr3);
  end
endmodule
2

I think only constraint c0 is sufficient to generate unique values in 3 different arrays.

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