Hello, everybody, i’m novice in UVM SystemVerilog. I trying to understand making my own practice based on Tinyalu core that simply make operation (add,and,xor) in one cycle clock and mul in three cycles over operand in 8 bits unsigned.
The objetives is make an Agent with the next components: 1-command_monitor(receive command from interface throught write_command function and send the command(command transaction) to subscribers with a uvm_analysis_port (put)).
2-result_monitor(idem before component, but using result transaction)
3-Coverage subscriber #(command transaction).
4-Scoreboard subscriber # (coommand/result transactions)
5- tester(put_port) → fifo → (get_port)driver–> write tinyalu_bfm optionally configuration using is_active (uvm_active_passive_enum)
Basically the chapter is about understand UVM agent concept; the test instanciate two agents and two tinyalu designs, the first is_active ACTIVE, and second is_active PASSIVE because the stimulus use an module called tester_module(virtual tinyalu bfm).
tinyalu_agent_cfg:
class tinyalu_agent_cfg ;
virtual tinyalu_bfm bfm ;
protected uvm_active_passive_enum is_active;
function new(virtual tinyalu_bfm bfm, uvm_active_passive_enum is_active);
this.bfm =bfm ;
this.is_active=is_active;
endfunction
function uvm_active_passive_enum get_is_active();
return is_active;
endfunction
endclass: tinyalu_agent_cfg
class tinyalu_agent extends uvm_agent;
`uvm_component_utils(tinyalu_agent)
tinyalu_agent_cfg tinyalu_agent_cfg_h ;
scoreboard scoreboard_h ;
coverage coverage_h ;
result_monitor result_monitor_h ;
command_monitor command_monitor_h ;
tester tester_h ;
driver driver_h ;
uvm_tlm_fifo #(command_transaction) command_f ;
uvm_analysis_port #(command_transaction) cmd_ap ;
uvm_analysis_port #(result_transaction) result_ap ;
function new(string name=“”,uvm_component parent) ;
super.new(name,parent) ;
endfunction
function void build_phase(uvm_phase phase);
if(!uvm_config_db#(tinyalu_agent_cfg)::get(this,"","config",tinyalu_agent_cfg_h))
`uvm_fatal("Tinyalu agent","Failed to get agent config")
is_active=tinyalu_agent_cfg_h.get_is_active();
if(get_is_active()==UVM_ACTIVE)
begin:make_stimulus
command_f=new("command_f",this) ;
tester_h=tester::type_id::create("tester_h",this);
driver_h=driver::type_id::create("driver_h",this);
end
scoreboard_h =scoreboard::type_id::create("scoreboard_h",this) ;
coverage_h =coverage::type_id::create("coverage_h",this) ;
result_monitor_h =result_monitor::type_id::create("result_monitor_h",this) ;
command_monitor_h=command_monitor::type_id::create("command_monitor_h",this);
cmd_ap =new("cmd_ap",this) ;
result_ap =new("result_ap",this) ;
endfunction
function void connect_phase(uvm_phase phase) ;
if(get_is_active()==UVM_ACTIVE)
begin:make_connections
driver_h.command_port.connect(command_f.get_export) ;
tester_h.command_port.connect(command_f.put_export) ;
end
command_monitor_h.ap.connect(cmd_ap) ;
result_monitor_h.ap.connect(result_ap) ;
command_monitor_h.ap.connect(scoreboard_h.cmd_f.analysis_export);
command_monitor_h.ap.connect(coverage_h.analysis_export) ;
result_monitor_h.ap.connect(scoreboard_h.analysis_export) ;
endfunction
endclass
********************Finally the Modelsim 10.6d stop the simulation **************************
End time: 12:53:09 on Oct 04,2023, Elapsed time: 0:01:24
Errors: 0, Warnings: 0
*********** IMPORTANT RELEASE NOTES ************
You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See 404 for more details.
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with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
See 404 for more details.
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UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
UVM_INFO @ 0: reporter [RNTST] Running test dual_test…
UVM_FATAL tb_classes/tinyalu_agent.svh(25) @ 0: uvm_test_top.env_h.class_agent_h [Tinyalu agent] Failed to get agent config
I don`t no why !!!