SV Proability Constraint for Number of Set Bits

SystemVerilog
1

Write a constraint for a 10 bit variable en so that; → 10% of the time 1 bit in en is high → 10% of the time 2 bits in en are high … → 10% of the time all 10 bits in en are high.

class sample;
  
  rand bit [10:1] en;
  
  constraint x{
    foreach(en[i])
    {
      $countones(en) == i dist {1:=10,0:=90};
    }
    
  }
  
endclass

Is my solution correct for this problem?

2

You can try this:

constraint x {
    $countones(en) dist {[1:10]:=1};
}
3 Likes
3

Shouldn’t it be

constraint x {
    $countones(en) dist {[1:10]:=10};
}
4 
class first;
  rand bit [9:0] en; 
  randc int b;
  constraint b_1 {
    			b >= 1;
  				b <=10;
    
  				}
  
  constraint en_1 {
    $countones(en) == b;
  				}
   
endclass
1 Like
5

I’m not sure if this a real good example for randomization.
I guess you want to see something like this

2 Likes
6

I think this will also work:

class sample;

rand bit [9:0] en;
//int i;

constraint x {$countones(en) dist {1:=10, 2:=10, 10:=10}; } ;

endclass

module top;

import uvm_pkg::*;
`include “uvm_macros.svh”

sample sc;

initial begin
sc = new();
for (int i = 0; i < 20; i++) begin
//sc.i = i;
sc.randomize();
`uvm_info(“TOP”, $sformatf(“en = %b”,sc.en), UVM_MEDIUM)
// sc.i++;
end
end

endmodule