Using std::randomize

SystemVerilog
,
1

Hi all,

Quick question on using std::randomize.

module randomize (

);

// variables given 
bit [31:0] address;

initial begin

    std::randomize(address) with {address[6:0]   == 7'b0000000;
                                  address[31:25] == 7'b0;
                                  address[14:12] == 3'b111;
                                 };

    $display("Address: %0b", address);
    $finish;
end

endmodule

I’m trying to constraint the following using std::randomize

  • First 7 bits of the 32-bit address to be all 0’s
  • the last 7 bits of the 32-bit address to be all 0’s
  • bits 12 to 14 to be 111 in the 32-bit address

But I managed to get the all but the last 7 bits of the 32-bit address to be all 0’s. It works on everything except setting all to 0’s.

Is there something that I did wrong?

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image973×321 25.7 KB

This was the result right after I ran my simulation on VCS

Sangwoo

1 Like
2

You did not display all 32 bits of address. I only see 25 bits displayed. The “%0b” format does not display the leading 0’s (in the MSBs).

Change:

    $display("Address: %0b", address);

to:

    $display("Address: %b", address);

I get:

Address: 00000001000001110111100000000000

3

Perhaps you didn’t check the number of bits, only 25 bits are printed. I’ve updated your example to also print the concerned bits:

module randomize ();
  
  // variables given 
  bit [31:0] address;
  
  initial begin
    repeat(10) begin
      std::randomize(address) with {
        address[6:0]   == 0;
        address[31:25] == 0;
        address[14:12] == '1;
      };
      
      $display("Address: %32b", address);
      $display("Address[6:0]: %7b", address[6:0]);
      $display("Address[31:25]: %7b", address[31:25]);
      $display("Address[14:12]: %3b", address[14:12]);
    end
  end
endmodule
4

What’s the difference between the “%0b” and “%b” display format?

5

I already explained that, but for more details refer to IEEE Std 1800-2017, 21.2.1.3 Size of displayed data.