How we can use task as function and function as task?

SystemVerilog
1

Recently, I have attended an interview for design verification role. In that interviewer asked me, how we can use function as task and task as function? Can anyone give me the answer for this question.

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2

This question is to make sure you understand the fundamental difference between functions and tasks in SystemVerilog.

  • tasks
    • may consume time
    • must be called as a statement in procedural code
  • functions
    • must not consume time(not have blocking statements)
    • may be used in an expression with a non-void return type.
    • must be called as a statement in procedural code with a void return type
      Tasks and functions have the same arguments syntax allowing inputs, outputs, defaults, etc. However, there are a number of places where functions are only allowed to have input arguments (i.e. inside random constraints)

It is highly recommended that you convert any task that does not consume time into a function with a void return type. This provides a guarantee to the caller that it will not block.

task printmetask;
  $display("hello");
endask
function void printmefunc;
  $display("hello");
endfunction

You should never write a function as a task, but for the purposes of this interview question you can do the example above in reverse

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