BUGGED OUT Podcast

In just 10–15 minutes per episode, host Harry Foster sits down with leading innovators, engineers, and researchers to talk about what’s shaping the future of verification — from AI-driven tools to design-for-test, coverage closure, reliability, and more. Expect candid conversations, practical insights, and a few “war stories” from the trenches of debug.

Whether you’re a verification engineer, a design lead, or simply curious about how we “get the bugs out” of the chips that power our world, BUGGED OUT delivers focused, informative conversations designed to fit your busy schedule.

Harry Foster returns with Part 2 of this special holiday edition of BUGGED OUT, continuing the exploration of how silicon and verification are rapidly evolving. In this episode, Harry looks at the forces accelerating change — from rising specialization and data-movement bottlenecks to growing power and security pressures that now shape system behavior. He also discusses how verification teams can scale as complexity increases, and why agentic AI and hybrid digital twins will become essential for unifying lifecycle-aware verification. Harry closes by sharing what these shifts could mean for engineering practices in 2026 — and beyond. To dive deeper into these themes, you can also download the companion white paper — The Future of Semiconductors: Engineering in the Convergence Era.

Harry Foster kicks off a special two-part holiday edition of BUGGED OUT with a look at the rapidly shifting landscape of modern silicon. He explores how innovation is moving above the transistor, why multi-die and software-defined systems are reshaping verification, and what it means when hardware continues evolving after it ships. Harry also shares his predictions for where the semiconductor and verification ecosystem is headed in 2026 — and beyond. To dive deeper into these themes, you can also download the companion white paper — The Future of Semiconductors: Engineering in the Convergence Era.

Harry Foster talks with Jacob Wiltgen, Director of IC Verification Solutions at Siemens EDA, about insights from his white paper Accelerating DFT Sign-off with Questa One. They explore why Design-for-Test is more critical than ever, how DFT sign-off bottlenecks can be relieved, and what mega-trends like scaling, reliability, and in-system test mean for the future of verification.

Harry Foster sits down with Tom Fitzpatrick to discuss insights from his white paper Better Stimulus Generation Through AI. Learn how Portable Stimulus and Questa One’s AI-driven assist are helping engineers overcome UVM’s limits, boost reuse, and accelerate verification productivity.