Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks

Welcome again to Verification Horizons.

In the last issue I wrote about my son graduating high school and my hopes for him as he begins his college career. Well, he's been at school (and away from home) for over six weeks at this point and seems to be off to a great start. We're going to visit him this weekend for the first time, and we're really looking forward to seeing him.

As he was preparing for college, my wife and I explained to him the importance of time management since, compared with high school where his days were pretty well defined from 7:00 AM until 3:00 PM (and sometimes later), he'd have much more free time and would have to use it effectively. When we spoke to him a few weeks ago, he told us that we were wrong because he really doesn't have much free time at all. Turns out he wasn't considering all of his extra-curricular activities, including playing the saxophone in the Jazz Ensemble and Pep Band and joining the Ultimate Frisbee team, to be "free time." Yes, his schedule is pretty packed, but he's having fun and still getting his homework done on time, so things are good.

This idea of taking full advantage of the time we have leads me into our first article, "How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology." The author shows us how to read the design specification to create appropriate assertions and coverpoints to improve verification efficiency by informing us how well we're doing throughout the process. By giving these elements names that link back to the specification, they can be even more useful in debugging the design.

Next, we have a trio of articles about different verification IP (VIP) components from my colleagues in our VIP Development Center in India.

The first article, is a relatively new protocol in "USB Type-C Verification: Challenges and Solution" where we learn about the interesting physical characteristics of USB Type-C. Because the USB Type-C connector is reversible and can connect to either hosts or devices, there are a number of new factors that must be verified, including mixed-signal issues. Our QVIP wraps all of these verification features in a convenient easy-to-use component that lets you verify and debug designs for this next generation of the USB standard.

We round out our QVIP session with "INs and OUTs of CAN Verification: A Comprehensive UVM-based Solution" in which we learn about the Controller Area Network (CAN) protocol, popular in automotive applications. As you'll see, there are a number of verification challenges inherent in the protocol that are handled easily by the QVIP component. I think you'll find interesting the discussion of our QVIP Configurator tool, a GUI-based tool that lets you generate an instance of the QVIP to fit in your specific UVM testbench environment.

Another aspect of efficient time management is to take full advantage of the resources you have. In "24x7 Productivity: Veloce® Enterprise Server App Does the Job," my colleague Vijay Chobisa, from Mentor's Emulation Division, shows us how this new software app makes Veloce emulation a trusted enterprise datacenter resource. In this article you'll learn about the powerful new features available for concurrent projects worldwide to enhance emulator usage and maximize not only your time, but your investment as well.

For those of you doing low-power design and verification, you'll find "Power Aware Libraries: Standardization and Requirements for Questa® Power Aware" to be particularly interesting. This article examines several different types of Power Aware l library cells and how they interact with the Unified Power Format (UPF) standard. You'll see how Questa PA-Sim can take advantage of some new Power Aware libraries to seamlessly augment your Power Aware verification.

We wrap up this issue with our Partners' Corner, from our friends at Arastu Systems, who share their thoughts on "Improving Performance and Verification of a System Through an Intelligent Testbench." The article shares their experience of verifying their DDR4 DRAM Memory Controller and how they created two new verification components to handle critical aspects of the verification. It's a slightly different interpretation of "Intelligent Testbench," but I think you'll find it valuable.

Now it's time for me to pack for my weekend trip to see David. I've been given some constraints and assertions by my wife, and I'm about to run to the store to fill some "coverage holes" for my travel kit. By the time you read this, I'll be home from my visit and looking forward to seeing him when he comes home for Thanksgiving. We're going to pack as much as we can into our time together this weekend. I hope you take some time to be with your family too.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons