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September 2021 - Volume 17 Issue 2 (12)

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July 2020 - Volume 16 Issue 2 (7)

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December 2019 - Volume 15 Issue 3 (5)

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November 2018 - Volume 14 Issue 3 (4)

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June 2017 - Volume 13 Issue 2 (2)

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March 2020

Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs
Formal Verification Mar 01, 2020 Tomáš Vaňák - Codasip Article
AI-Based Sequence Detection
Machine Learning Mar 01, 2020 Asif Ahmad, Abhishek Chauhan - Agnisys Article
An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems Article
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
Verification IP Mar 01, 2020 Dr. Nicole Fern - Tortuga Logic Article
Formal Verification of RISC-V® Processors
Formal Verification Mar 01, 2020 Dr. Ashish Darbari Article

January 2020

Reset Verification in SoC Designs
Clock-Domain Crossing Jan 07, 2020 Kurt Takara Article

December 2019

Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
Acceleration Dec 03, 2019 Jean-Marie Brunet Article
Deadlock Prevention Made Easy with Formal Verification
Formal Verification Dec 03, 2019 Dr. Jeremy Levitt Article
Exercising State Machines with Command Sequences
Standards Dec 03, 2019 Matthew Ballance Article
Designing A Portable Stimulus Reuse Strategy
Standards Dec 03, 2019 Matthew Ballance Article
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Clock-Domain Crossing Dec 03, 2019 Kurt Takara Article
Is Your Verification in Jeopardy?
Simulation Dec 02, 2019 Tom Fitzpatrick Article

July 2019

Visualizer™ Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!
Simulation Jul 17, 2019 Rich Edelman Article
Is It Magic, or Ingenious People Working with Remarkably Advanced Technology?
Simulation Jul 16, 2019 Verification Horizons Article

June 2019

SystemC FMU for Verification of Advanced Driver Assistance Systems
Functional Safety Jun 03, 2019 Keroles Khalil, Magdy A. El-Moursy - Siemens Eda Article
Fun with UVM Sequences - Coding and Debugging
UVM - Universal Verification Methodology Jun 03, 2019 Rich Edelman Article
Creating Tests the PSS Way in SystemVerilog
SystemVerilog Jun 03, 2019 Matthew Ballance Article
Formal Bug Hunting with “River Fishing” Techniques
Formal Verification Jun 03, 2019 Mark Eslinger Article
Auto-Generating Implementation-Level Sequences for PSS
Standards Jun 03, 2019 Amanjyot Kaur, Louie De Luna - Agnisys Article
UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs
UVM Framework Jun 03, 2019 George Stevens - Designlinx Solutions Article

March 2019

Debugging Inconclusive Assertions and a Case Study
Formal Verification Mar 28, 2019 Jin Hou Article

February 2019

Ten Rules to Successfully Deploy Formal
Formal Verification Feb 25, 2019 Dr. Ashish Darbari Article
Formal Apps Take the Bias Out of Functional Verification
Formal Verification Feb 25, 2019 Bill Au Article
Simplifying Assertion Validation Using UVM Callbacks
Assertions Feb 25, 2019 Arushi Jain - Siemens Eda Article
Effective Elements Lists and the Transitive Nature of UPF Commands
Low Power Feb 25, 2019 Progyna Khondkar Article

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Browse all content in Siemens Verification Academy with the tag verification horizons

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