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July 2020 - Volume 16 Issue 2 (5)

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December 2022 - Volume 18 Issue 3 (4)

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June 2019 - Volume 15 Issue 2 (4)

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March 2014 - Volume 10 Issue 1 (4)

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Metastability Injection (4)

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November 2015 - Volume 11 Issue 3 (4)

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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

March 2020 - Volume 16 Issue 1 (3)

Mathworks (3)

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December 2019 - Volume 15 Issue 3 (2)

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July 2023 - Volume 19 Issue 2 (2)

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March 2015 - Volume 11 Issue 1 (2)

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December 2017 - Volume 13 Issue 3 (1)

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October 2019

Why RDC Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara pdf

September 2019

Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden Session
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden pdf
Code Generation Guidelines
UVM Framework Sep 09, 2019 Bob Oden Session
Code Generation Guidelines
UVM Framework Sep 09, 2019 Jonathan Craft pdf

August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Machine Learning Aug 31, 2019 Brucek Khailany link
Coverage Driven Verification of NVMe Using Questa VIP
Verification IP Aug 21, 2019 pdf
Results Checking Strategies with Portable Stimulus
Portable Stimulus Aug 02, 2019 Tom Fitzpatrick pdf
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman pdf
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman Paper

July 2019

Improving Verification Throughput of Today’s Complex Mixed-Signal ICs
Analog Mixed-Signal Jul 12, 2019 pdf
Selecting the Most Productive SoC Design Verification Techniques
Planning, Measurement and Analysis Jul 12, 2019 pdf
RISC-V Core and SoC: Compliance, Verification, Customization
Verification IP Jul 11, 2019 Larry Lapides pdf
Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity
Portable Stimulus Jul 11, 2019 Tom Fitzpatrick pdf

June 2019

Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models
Coverage Jun 15, 2019 Thomas Ellis pdf
Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models
Coverage Jun 15, 2019 Thomas Ellis Paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
Clock-Domain Crossing Jun 11, 2019 Kurt Takara pdf
A Specification-Driven Methodology for the Design and Verification of RDC Logic
Reset-Domain Crossing Jun 11, 2019 Kurt Takara Paper
Reusable UPF - Transitioning from RTL to Gate Level Verification
Low Power Jun 11, 2019 pdf
What's Missing and What Should Be Next for SystemVerilog
SystemVerilog Jun 03, 2019 Cliff Cummings pdf
Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer
Debug Jun 03, 2019 Sumit Vishwakarma pdf
Debugging Your Design in a Heterogeneous Environment
Debug Jun 03, 2019 Rich Edelman pdf
Debugging Your Design in a Heterogeneous Environment
Debug Jun 03, 2019 Rich Edelman Conference
Fun with UVM Sequences: Coding and Debugging
UVM - Universal Verification Methodology Jun 03, 2019 Rich Edelman Article
Creating Tests the PSS Way in SystemVerilog
Portable Stimulus Jun 03, 2019 Matthew Ballance Article

FPGA Webinar

Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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