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What Does Improving Your Golf Swing Have in Common with Verification?
I may have mentioned over the years that I am an avid golfer. In order to have an excuse to play weekly, I joined a local golf league last year, and this year's season just started. In an effort to improve my swing, and consequently my score, I decided to start this season by taking a lesson with the pro at my local course. After looking at my swing, the pro told me he was going to make four small changes to my swing and could guarantee that my score will improve by 10 shots per round. He showed me the four things, and they all make sense. Some of them are easy, like changing my grip slightly. Some are harder, like keeping a steeper wrist angle during my downswing. Let's just say that, since I haven't reliably been able to do everything he told me yet, I haven't achieved the promised results, although when I played earlier this week I did hit a number of very good approach shots. So, I'm encouraged.
In golf, I have an objective measurement of how well I'm doing: my score. I also have a nice app for my phone that lets me track various statistics so I can see where I need to improve (like my putting). Of course, my experience is also an example of the difference between being taught something new and actually being able to apply it to your situation. Sounds a lot like verification, doesn't it? (You knew I was going to get there, didn't you?)
We start off this issue with a really interesting article by my colleague Hamilton Carter of our Mentor Consulting Division, who has gotten some great results in applying "Big Data" analysis techniques throughout the verification process. In "Parallel Debug: A Path to a Better Big Data Diaspora," Hamilton walks us through a new parallel debug methodology and shows how to deploy it using the Questa® Verification Run Manager and our new Jenkins plugin. The discussion about how to deliver on the promise of Big Data will leave you with a great vision of the possibilities in this exciting new area of analysis.
We next have two articles about how you can apply Portable Stimulus at different points to improve reuse throughout your verification flow. In "Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow," we'll see how you can generate the exact same stimulus for both a high-level C++/SystemC model of your system and for the RTL representation as well, including making sure that you achieve full coverage on your HLS model before generating the RTL.
The second article is "Smoothing the Path to Software-Driven Verification with Portable Stimulus" by our resident Portable Stimulus guru, Matthew Ballance. Since the key to software-driven verification is to first make sure that your processor can successfully read and write your hardware registers before trying to run full-blown applications, Matthew shows us how to use a declarative graph-based approach (on which the new Accellera Portable Stimulus Standard is based) to take a step-wise path to verifying all of the interactions early in the integration process. Being able to generate both UVM and C tests from this stimulus model simplifies the overall process and makes you more productive.
We move into our "Partners' Corner" section with "Verification Planning with Questa Verification Management" from our friends at eInfochips. In this article you'll see how to take advantage of the Questa Testplan Tracking feature to track regression results, coverage and other valuable information. The authors also share some tips on how to apply this tracking process to make it easier to apply to your verification project.
In "MIPI® CSI2 TX IP Verification Using Questa VIPs," our friends at HDL Design House discuss how they used Questa VIP (QVIP) components to verify a Camera Serial Interface 2 design. You'll see how they set up their UVM environment and were able to take advantage of the documentation and ease-of-use features of QVIP to reduce their testbench development time. They now consider these QVIP components to be golden models, so they don't have to worry about them in future projects.
We move into the area of power-aware verification with "Converting Legacy USB IP to a Low Power USB IP" from our friends at Silicon Interfaces. If you've been wondering how to apply low-power techniques to your next design, and verify that you've done it correctly, you'll want to read about what they've done. For more details on how actually to apply UPF for specifying different power domains, you'll want to read "Understanding the UPF Power Domain and Domain Boundary" from my Mentor colleague Progyna Khondkar (which we sneaked into the Partners' Corner anyway).
We round out the Partners' Corner with "Automation and Reuse in RISC-V Verification Flow," by our friends at Codasip. In this comprehensive case study, Codasip shows you how several pieces of the Questa® Verification Solution can be used with an automatically-generated UVM environment and associated infrastructure to reduce the length of a verification project substantially.
If you've been reluctant to add emulation to your verification process (like your competitors probably already have), our next article, "Emulation – A Job Management Strategy to Maximize Use" by Vijay Chobisa, one of our Mentor emulation experts, provides a point-by-point discussion of why emulation is important and how to overcome the usual objections to taking this important step. The key is the use of our new Veloce® Enterprise Server app that optimizes use of the emulator by providing flexible resource sharing with no extra work on your part.
Next, our formal verification team explains that "RTL CDC is No Longer Enough—How Gate-Level CDC Is Now Essential to First Pass Success." This article shows how synthesis can introduce clock-domain crossing errors and how applying CDC verification at the gate-level can prevent them from making it into your silicon. The key is that it uses knowledge from the RTL CDC process to make it easier and faster to eliminate these critical bugs.
In our Consultants' Corner article, Siemens EDA consultant Rusty Stuber explores "Formal Verification: Not Just for Control Paths." You'll see how a few straightforward techniques, like adding some SystemVerilog helper constructs and using targeted protocol assumptions, allows you to write effective assertions about the datapath portions of your design and limit the state space to enable full verification of your entire datapath. I think you'll find this detailed how-to discussion to be incredibly helpful.
Unfortunately, I'll be too busy at DAC to try out my new golf swing while I'm in Austin, but if you see me swinging the microphone at the Verification Academy booth (#429), you'll know why. I hope you'll come by and say hi and stick around for a great slate of presentations by our partners, Siemens EDA experts, and "yours truly." It'll be a great week of informative fun, and I hope to see you there.
Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons
June 2017
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Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow
Standards Jun 28, 2017 Article -
Smoothing the Path to Software-Driven Verification with Portable Stimulus
Standards Jun 28, 2017 Article -
Verification Planning with Questa Verification Management
Verification Management Jun 28, 2017 Article -
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Automation and Reuse in RISC-V Verification Flow
UVM - Universal Verification Methodology Jun 28, 2017 Article -
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RTL CDC is No Longer Enough: How Gate-Level CDC is Now Essential to First Pass Success
Clock-Domain Crossing Jun 28, 2017 Article -