New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow

Portable Stimulus has become quite the buzz-word in the verification community in the last year or two, but like most 'new' concepts it has evolved from some already established tools and methodologies. For example, having a common stimulus model between different levels of design abstraction has been possible for many years with graph-based stimulus automation tools like Questa inFact.

Mike Andrews, Mike Fingeroff - Siemens EDA

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