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Handling Inconclusive Assertions in Formal Verification

In this track, you will be introduced to techniques to help formal tools solve inconclusive assertions. You will also learn tool options to help convergence, introduce techniques for reducing assertion and design complexity.

  • Formal Verification

Jin Hou

Last Updated Oct 2017
  • Assertions
  • Convergence
  • Error Traces
  • Formal Verification
  • Inconclusives
  • Proofs
  • Property Checking
  • Design Complexity
  • Non-Determinism
  • Bug Hunting
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  • Handling Inconclusive Assertions in Formal Verification
  • 1. Editor Insight
  • 2. Easy Solutions
  • 3. Assertion Complexity Reduction
  • 4. Design Complexity Reduction
  • 5. Advanced Topics
  • Sessions

    • Editor Insight

      This editor insight session provides an introduction and motivation for our new track, which is focused on handling inconclusive assertions in formal property checking.

      Track Oct 10, 2017 by Harry Foster

      • Formal Verification

    • Easy Solutions

      In this session you will be introduced to easy solutions for handling inconclusive assertions by exploring tool options, and how to know where formal is stuck at.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

    • Assertion Complexity Reduction

      In this session you will be introduced to the techniques that reduce the complexity of assumptions and checkers for formal verification, including under-constraining, over-constraining, assertion decomposition, adding “helper” assertion, assume-guarantee, and Questa® QFL assertion libraries.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

    • Design Complexity Reduction

      In this session, you will be introduced to techniques to reduce the complexity of designs for formal verification, including understanding what formal is analyzing, easy ways to reduce design complexity, counter remodeling and memory remodeling examples.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

    • Advanced Topics

      In this session, you will be introduced to the techniques of separating functions, data-independence, non-determinism, and bug hunting that are very useful for formal verification.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

  • Overivew

    Assertion-based formal verification can fully verify the functions of a design if all of the associated assertions can converge. Formal verification doesn’t need testbenches and can start much earlier in the process. It can consider all possible input stimulus sequences to find error traces of assertions or prove the assertions if no stimulus sequence can violate the assertions. The proof capability of formal doesn’t exist in simulation. More and more companies are adopting formal verification.

    However, due to the complexity of designs we have today, almost inevitably the user will encounter non-convergence problems which occur when the tools are unable to find either proofs or error traces for some assertions. Capacity limitations are a well-known characteristic of today’s formal verification tools. Fortunately, designers and verification engineers can learn methods for analyzing these non-convergence problems and improving their verification results.

    In this track, the instructor Jin Hou will introduce the techniques to help formal tools solve inconclusive assertions. She will show how to use tool options to help convergence, introduce techniques for reducing assertion and design complexity. She will also introduce advanced ND and DI techniques for reducing formal complexity, how to verify different functions separately, and bug hunting methods. Using these techniques, the user can get more results from formal tools.

  • Forum Discussion - Assertions

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      Mar 18, 2025 SystemVerilog
    • SV bind and Part compilation

      Mar 16, 2025 SystemVerilog
    • Write assertion and both cases need to be satisfied in single property Note: when signal B toggles signal A should be stable and should satisfy rise and fall of signal B also

      Manikanta_62 Mar 13, 2025 SystemVerilog
    • Constraint to make sure each value gets randomized at least once

      Xaiver Mar 12, 2025 SystemVerilog
    • Binding a module to another module's modport interface

      varunr86 Mar 06, 2025 SystemVerilog
    • PDF version of SVA Handbook 4th Edition now available

      hdlcohen Mar 01, 2025 Announcements
    • Assertion coding for a random pattern

      AK3 Feb 27, 2025 SystemVerilog
    • Overlap between the two asynchronous reset signals

      Redfoo Feb 27, 2025 SystemVerilog
    Join the Assertions Discussion
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