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  3. Formal Verification

Handling Inconclusive Assertions in Formal Verification

In this track, you will be introduced to techniques to help formal tools solve inconclusive assertions. You will also learn tool options to help convergence, introduce techniques for reducing assertion and design complexity.

  • Formal Verification

Jin Hou

Last Updated Oct 2017
  • Assertions
  • Convergence
  • Error Traces
  • Formal Verification
  • Inconclusives
  • Proofs
  • Property Checking
  • Design Complexity
  • Non-Determinism
  • Bug Hunting
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  • Handling Inconclusive Assertions in Formal Verification
  • 1. Editor Insight
  • 2. Easy Solutions
  • 3. Assertion Complexity Reduction
  • 4. Design Complexity Reduction
  • 5. Advanced Topics
  • Sessions

    • Editor Insight

      This editor insight session provides an introduction and motivation for our new track, which is focused on handling inconclusive assertions in formal property checking.

      Track Oct 10, 2017 by Harry Foster

      • Formal Verification

    • Easy Solutions

      In this session you will be introduced to easy solutions for handling inconclusive assertions by exploring tool options, and how to know where formal is stuck at.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

    • Assertion Complexity Reduction

      In this session you will be introduced to the techniques that reduce the complexity of assumptions and checkers for formal verification, including under-constraining, over-constraining, assertion decomposition, adding “helper” assertion, assume-guarantee, and Questa® QFL assertion libraries.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

    • Design Complexity Reduction

      In this session, you will be introduced to techniques to reduce the complexity of designs for formal verification, including understanding what formal is analyzing, easy ways to reduce design complexity, counter remodeling and memory remodeling examples.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

    • Advanced Topics

      In this session, you will be introduced to the techniques of separating functions, data-independence, non-determinism, and bug hunting that are very useful for formal verification.

      Track Oct 10, 2017 by Jin Hou

      • Formal Verification

  • Overivew

    Assertion-based formal verification can fully verify the functions of a design if all of the associated assertions can converge. Formal verification doesn’t need testbenches and can start much earlier in the process. It can consider all possible input stimulus sequences to find error traces of assertions or prove the assertions if no stimulus sequence can violate the assertions. The proof capability of formal doesn’t exist in simulation. More and more companies are adopting formal verification.

    However, due to the complexity of designs we have today, almost inevitably the user will encounter non-convergence problems which occur when the tools are unable to find either proofs or error traces for some assertions. Capacity limitations are a well-known characteristic of today’s formal verification tools. Fortunately, designers and verification engineers can learn methods for analyzing these non-convergence problems and improving their verification results.

    In this track, the instructor Jin Hou will introduce the techniques to help formal tools solve inconclusive assertions. She will show how to use tool options to help convergence, introduce techniques for reducing assertion and design complexity. She will also introduce advanced ND and DI techniques for reducing formal complexity, how to verify different functions separately, and bug hunting methods. Using these techniques, the user can get more results from formal tools.

  • Forum Discussion - Assertions

    • Liveness and safety property in formal verification

      Ktk_1711 May 28, 2025 SystemVerilog
    • SystemVerilog Assertions Free/Symbolic Variable Usage Error

      V_Rohith May 22, 2025 SystemVerilog
    • Issue with Defining a 2D Non-Deterministic Array in Formal Verification Property

      PNK May 21, 2025 SystemVerilog
    • Access internal reg and local param of the RTL from the sva file

      nch May 21, 2025 SystemVerilog
    • Assertion for 55mhz clock

      Surya_prakash.Kapireddy May 19, 2025 SystemVerilog
    • SVA assertions and preponed region evaluation

      JGu May 18, 2025 SystemVerilog
    • Common uvm_sequence for multiple sequence_items

      May 17, 2025 UVM
    • Query regarding witness for vacuosly passing assertions in Formal Verification

      Ktk_1711 May 16, 2025 SystemVerilog
    • `randc` not legal with `solve`

      stefaniemcg May 16, 2025 Coverage
    • Can anyone help to write assertion for 200MHz clk check?

      indrajeetpande May 15, 2025 UVM
    • Write an SVA - if signal b rose high then in the past {x:y] cycle signal a should be high . I am only aware of $past which checks at a particular cycle in the past , how to take care in case we need to check for few cycles in the past

      _piyush.mishra May 14, 2025 SystemVerilog
    • Assertion to check reset is synchronised to the input clock

      ShilpiM May 13, 2025 SystemVerilog
    • Simulation-based verification with nondeterminism

      May 09, 2025 UVM
    • Constraint for 101 pattern

      May 08, 2025 SystemVerilog
    • How to use SVA to check whether a multi-bit signal is going to change within 100 nanoseconds after the arrival of a signal rising edge?

      May 07, 2025 SystemVerilog
    • How to Ignore multiple bins in the function coverage using binsof & intersect?

      desperadorocks May 07, 2025 SystemVerilog
    • Questions on disable iff

      LFT Apr 30, 2025 SystemVerilog
    • Working of strong operator & final block

      LFT Apr 29, 2025 SystemVerilog
    • Formal Assumption to Model a FIFO Push (with a delay)

      gitosman Apr 27, 2025 SystemVerilog
    • Power aware verification

      zoro Apr 11, 2025 UVM
    Join the Assertions Discussion
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