Immediate assertion not taking either of its action blocks

SystemVerilog
1

I have code that looks something like this:

initial begin
    @(go);
    $display("Checking...");
    assert(tb.dut.inst1.inst2.a == 'h42)
        $display("PASS");
    else
        $fatal("FAIL");
end

When the go signal changes, I see “Checking…” printed to the log file, but neither “PASS” nor “FAIL”. The a signal deep in the DUT hierarchy is assigned a literal that should be 0x42.

Why did neither action block execute in this simpified and contrived example?

2

Check if there are “Assertion control system tasks” in your Tb

module tb;
 
 bit          go; 
 logic [9:0]  a;
   
 initial begin
   #10   a = 'h42; 
        go = 1;
 end
  
 initial begin:I2
    @(go);
    $display("Checking...");
    assert(tb.a == 'h42)
        $display("PASS");
    else
        $display("FAIL");
  end:I2
  
endmodule

Case1 :: Using $assertoff

 initial 
   $assertoff(0,tb.I2);  // Won't display either "PASS" or "FAIL"

Case2 :: Using $assertpassoff & $assertfailoff

 initial begin 
    $assertpassoff(0,tb.I2);  // Won't display "PASS"
    $assertfailoff(0,tb.I2);  // Won't display "FAIL"
 end
3

There are no assertion control system tasks/functions in the TB nor are there any assertion options passed on the command-line to disable assertions.

It’s strange and I’ve gone through the relevant parts in the LRM with attention to detail.

4

Upon further digging around the TB, I found an $assertkill on the module containing the assertions in question. I think this is the cause. Thanks for the feedback on the assertion control. It did help lead to this.