Accessing invalid address is not working

SystemVerilog
1

Hi,

Below is small logic for accessing invalid address in case of APB slave verification using systemverilog.

if(enable_wr_invalid_addr_task) begin // accessing invalid address
      apb_transaction trans = new();
      assert(trans.randomize());
      trans.kind = apb_transaction::APB_WRITE;
      trans.addr = `MEM_DEPTH + 4;
       $display("Addr value:0x%h", trans.addr);
      trans.wdata = 8'hDE;
      mbox.put(trans);

while some defines are below which i am using:

`define ADDR_WIDTH 8
`define DATA_WIDTH 8
`define MEM_DEPTH 2**(`ADDR_WIDTH)

some constraints which i am using:

constraint aligned_addr_c { addr[1:0] == 2'b00; }
constraint valid_addr_c { addr inside {[0:`MEM_DEPTH-1]};}

In the above code, trans.addr is not taking the value of `MEM_DEPTH, it is only taking the value of 4. Please guide, i am trying to access the invalid address beyond 0-256 since addr is 8 bit.

2

You should post a complete example which demonstrates your issue. It’s difficult to determine what is wrong without seeing all variables declared.

You state that you want to access address >256, but address is only 8 bits which allows only 0 -255. What are you trying to accomplish and what isn’t working?

3

In the apb_generator, i am writing testcases in the task, and enabling them at the top of this file. Now, i am writing testcase to check the invalid address. But the trans.addr in the task is not taking the value which i am assigning in the task. Please guide.

4

In the above, trans.addr is not taking the value of MEM_DEPTH define, it is only taking value 4 which i am adding to MEM_DEPTH. I am trying to access the invalid address range of 8 bit address. Please guide.

5

Again, it would be very helpful if you show the complete code you are using, including variable definitions. If trans.addr is only 8 bits wide, then it can only have values 0 to 255. You can’t have any addr value outside of that range.

6

Hi Cgales,

Please guide, how to write the testcase in systemverilog for writing and reading to invalid address for below memory:

  logic [31:0]mem[256]. // Here we can write 32 bit data to 255 different  locations.
7

The address bus to your APB slave is 8 bits, which means addresses 0 to 255. Your memory supports 256 addresses, 0 to 255. Your address bus will always contain a valid address.

You have two options:

  1. Make your APB slave address bus bigger than 8 bits.
  2. Make your memory smaller than 256 elements.