Poll for a status register until we see desired read value

SystemVerilog
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1

Hi,
There is a test sequence which performs random number of writes/reads & then we need to check the read value of a status register. There are three fields in this register: busy, complete & error - each 1 bit. So, when the writes or reads start the busy bit is set and after all the writes or all the reads get completed we see the complete bit set. Currently I have something like this:

while(!complete) begin
read_reg(....);
complete = read_data[1];
error = read_data[2];
wait_clocks(n)
end

But, since the complete field is set only for one cycle I can miss that particular cycle when I read after n clocks delay. Is this a valid or not ? If yes, could someone please tell me how can one avoid this.
image

2

A few questions ::

(Q1) Wouldn’t ‘read_reg’ take a few clocks (due to handshake b/w Master & Slave) to complete ?
If yes, one could possibly miss the complete signal when asserted

(Q2) What was the intention behind using wait_clocks(n) ?

A backdoor read is one possible solution

while(!complete) begin
 STS_reg.read(status,rd_data,UVM_BACKDOOR);
    error = rd_data[2];
 complete = rd_data[1]; 
 if(!complete) #(TCLK);  // To avoid infinite loop when complete is de-asserted
end

I believe the DUT should keep the busy/complete/error fields asserted till Read operation is performed.

3

Thanks for answering.
The intention behind using the wait_clocks(n) was to avoid frequent reads, I was not aware that the complete/error field would be set for single cycle when I initially wrote this. Still not sure if it is correct way.
And I understood that even without delays there is a possibility to miss that particular cycle if we use the frontdoor read.
The correct solution as you suggested is that fields should be asserted until they are read.