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December 2025

Aerospace & Defense
Functional Safety Dec 03, 2025 Todd Holbrook Reference

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

Browse all Intermediate content in Siemens Verification Academy

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December 2025

Aerospace & Defense

November 2025

HLV: Formal Verification of Synthesizable C++/SystemC Designs

HLV: Formal Verification of Synthesizable C++/SystemC Designs

October 2025

Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities

Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities

Combining Performance and Formal Security Guarantees for Hardware Accelerators

Combining Performance and Formal Security Guarantees for Hardware Accelerators

Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification

Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification

Adaptable FWHW Formal Co-Verification of SoC RISC-V Components

Adaptable FWHW Formal Co-Verification of SoC RISC-V Components

Formally Verifying Security Properties of CHERI Hardware and Software

Formally Verifying Security Properties of CHERI Hardware and Software

Harnessing AI for Real-world Hardware Verification

Harnessing AI for Real-world Hardware Verification

Stimulus Free Verification of a Clock Bridge Using Static and Formal

Stimulus Free Verification of a Clock Bridge Using Static and Formal

osmosis Europe 2025

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP

Breaking Silos: Creating Synergistic Flows for Next-Gen Verification

Breaking Silos: Creating Synergistic Flows for Next-Gen Verification

September 2025

From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025

No Reset? No Worries! Smarter Ways to Tackle RDCs to NRRs

Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs