UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, “Better Living Through Better Class-Based SystemVerilog Debug”) and the unique debug facilities in the Questa Verification Platform.
This Verification Cookbook seminar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
