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Market-Driven Trends in Hardware Emulation
Webinar - May 21, 2020 by Vijay Chobisa
In this session you will learn how AI/ML, 5G, networking and ADAS designs are affecting verification and validation and how Veloce Strato & VirtuaLAB address these verification challenges.
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Context-Aware Debug
Webinar - May 21, 2020 by Rich Edelman
In this session, you will learn how to utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).
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Productivity in the Questa Simulation Flow
Webinar - May 15, 2020 by Gordon Allan
In this session, you will learn every step of the Questa Simulation-based verification flow has been optimized and accelerated, from regression management, to incremental compilation and elaboration, to debug and coverage.
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Optimizing Time to Bug
Webinar - May 15, 2020 by Tom Fitzpatrick
In this session, we'll be highlighting the issues that have cropped up in recent years, including the explosion in the amount of data that must now be verified and managed and the safety and security of the data and systems they control.
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ISO 26262 Requirements Management
Session - Apr 21, 2020 by Jacob Wiltgen
In this session, you will learn the workflow of a requirement, the artifacts that must be captured to successfully pass an assessment, and the importance of automated data management.
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ISO 26262 in Simple Terms
Session - Apr 21, 2020 by Jacob Wiltgen
In this session, you will gain an understanding of the core mission, scope, and key concepts of ISO 26262.
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ISO 26262 in Simple Terms
Resource (Slides) - Apr 21, 2020 by Jacob Wiltgen
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ISO 26262 Requirements Management
Resource (Slides) - Apr 21, 2020 by Jacob Wiltgen
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Introduction to ISO 26262
Track - Apr 20, 2020 by Jacob Wiltgen
The purpose of this track is to provide engineers and managers with a basic understanding of the key concepts of ISO 26262. This includes information on the scope of the standard, how the standard addresses the broader automotive supply chain, and key requirements defined at each phase of the product lifecycle.
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UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know
Webinar - Apr 10, 2020 by Chris Spear
In this session, you will learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs.
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Code Generation Merging
Resource (Slides) - Apr 01, 2020 by Jonathan Craft
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Code Generation Merging
Session - Apr 01, 2020 by Jonathan Craft
In this session you will learn about UVMF code generation capabilities that allow you to quickly produce new iterations of generated code that automatically transfer previous manual edits from earlier versions.
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Mind the GAP(s): Closing and Creating GAPS Between Design and Verification
Resource (Slides) - Mar 31, 2020 by Chris Giles
This workshop will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.
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Mind the Gap(s): Closing and Creating Gaps Between Design and Verification
Webinar - Mar 31, 2020 by Chris Giles
This session will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.
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FPGA Verification Maturity: A Quantitative Analysis
Webinar - Mar 26, 2020 by Harry Foster
While multiple studies on IC/ASIC functional verification trends have been published, there have been no studies specifically focused on FPGA verification trends. To address this dearth of information, Harry presents the results from a recent large industry study on functional verification.
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FPGA Verification Maturity: A Quantitative Analysis
Resource (Slides) - Mar 26, 2020 by
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Verify Thy Verifyer
Article - Mar 01, 2020 by Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks
Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases. The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches.
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Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs
Article - Mar 01, 2020 by Tomáš Vaňák - Codasip
Questa SLEC, the formal analysis app from Siemens EDA, was designed to automatically compare a block of code ("specification" RTL) with its functional equivalent that has been slightly modified ("implementation" RTL), helping design teams save considerable amounts of time and resources. Codasip, the leading provider of configurable RISC-V® IP, has come up with a new use of this tool: the verification team uses it to compare a fully UVM-verified HDL code.
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AI-Based Sequence Detection
Article - Mar 01, 2020 by Asif Ahmad, Abhishek Chauhan - Agnisys
In this era of automation, significant advantages can be gained by automatically generating verification and validation sequences from natural language text using artificial intelligence (AI) based sequence detection techniques, and then using those sequences in C/UVM code. This article talks about the current state of development in this area and gives ideas about how you can implement your own solution to achieve true specification-driven software development.
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An Open Data Management Tool for Design and Verification
Article - Mar 01, 2020 by Vishal Patel, Manoj Pandey - Arastu Systems
The Big Data technology has evolved to handle both volume and velocity of data, currently being generated by the chip design and verification activities. The core challenge of effective data management and hence actionable insight generation is still not available to the industry in the true sense. Connecting data islands as created by various tools in various formats across digital design and verification workflows and creating a Unified Data Lake is an important missing piece.
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Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
Article - Mar 01, 2020 by Dr. Nicole Fern - Tortuga Logic
Modern electronic systems are complex, and economics dictate that the design, manufacturing, testing, integration and deployment of Application Specific Integrated Circuits (ASICs), System on Chips (SoCs) and Field Programmable Gate Arrays (FPGAs) span companies and countries. Security and trust in this diverse landscape of 3rd party IP providers, processor vendors, SoC integrators and fabrication facilities, is both challenging and introduces security risks.
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Formal Verification of RISC-V® Processors
Article - Mar 01, 2020 by Dr. Ashish Darbari
The verification of modern-day processors is a non-trivial exercise, and RISC-V® is no exception. In this article, we present a formal verification methodology for verifying a family of RISC-V® “low-power” processors. Our methodology is both new and unique in the way we address the challenges of verification going beyond just functional verification.
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Reset Verification in SoC Designs
Article - Jan 07, 2020 by Kurt Takara
Modern system-on-chip (SoC) designs contain a high level of complexity in the reset distribution and synchronization circuitry. Verifying that a design can be correctly reset under all modes of operation presents a significant challenge. In this article, we present the commonly occurring issues that are involved in reset tree verification and solutions to address them.
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Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
Article - Jan 07, 2020 by Matthew Ballance
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Article - Jan 07, 2020 by Joe Hupcey