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  • Connecting Env to DUT

    This session explains how to connect a UVM testbench to the DUT and how to share information around the testbench using the configuration database.

  • Connecting Components | Japanese

  • Connecting Components

  • Connecting Components

    This session explains the phases of a UVM component, focusing on how to use the build and connect phases.

  • Introducing Transactions

    This session explains how to use transactions to communication between a sequencer and a driver in UVM.

  • Introducing Transactions | Japanese

  • Introducing Transactions

  • Sequences and Tests

    This session explains how to create sequences of transactions, sequences of sequences, and how to start a sequence from a test.

  • Sequences and Tests | Japanese

  • Sequences and Tests

  • Monitors and Subscribers

  • Monitors and Subscribers | Japanese

  • Monitors and Subscribers

    This session explains how to create passive components such as monitors and subscribers, and how to connect them using analysis ports.

  • Reporting

  • Reporting | Japanese

  • Reporting

    This session explains message reporting in UVM, and shows simple ways in which reporting can be customized.

  • UVM Basics

    UVM Basics will raise a user's level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.

  • Architecting a UVM Testbench

    This session covers the basic architecture of a UVM testbench, including the introduction of the Agent/UVC component.

  • Architecting a UVM Testbench

  • Understanding the Factory and Configuration

  • Understanding the Factory and Configuration

    This session shows how tests can use the factory to control the type of components that get instantiated in a UVM environment.

  • Modeling Transactions

    This session outlines the methods needed in the design of a sequence item (a.k.a. “transaction") for use in UVM.

  • Modeling Transactions

  • How TLM Works

  • How TLM Works

    This session discusses the use of TLM interfaces in UVM to facilitate the creation of modular, hierarchical components.