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1963 Results

  • The Future of Automotive and its Impact on Safety

    This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.

  • Creating a Fast and Productive USB4 Verification Environment

    This session walks through the step-by-step workflow to integrate Questa Verification IP (QVIP) – USB4 into a testbench. The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP, thereby reducing the testbench development efforts, and also the efforts needed for integrating QVIP into an existing testbench.

  • It’s Not My Fault! How to Run a Better Fault Campaign Using Formal

    The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing.

  • Part II: Verification of PCIe® IP

    In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.

  • UVM Framework Release 2021.3

    General Updates: General bug fixes and documentation updates Generator Updates: Added C data types for Mathworks® integration flow

  • Sequential Logic Equivalence Checking

    In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

  • SLEC Introduction

    In this session, you will learn the concept of sequential logic equivalence checking (SLEC) and the common applications of SLEC.

  • SLEC for Design Optimization

    In this session, you will learn how to use SLEC to verify functional equivalence between two RTL designs before and after optimization.

  • SLEC for Bug Fix / ECO

    In this session, you will learn how to use SLEC to verify that bug fix/ ECO doesn’t introduce new bugs.

  • SLEC for Low Power Clock Gating

    In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.

  • SLEC for Safety Mechanism

    In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.

  • Formal Verification for DO-254 (and other Safety-Critical) Designs

    This document focuses on the issue of advanced verification and tool assessment for DO-254, specifically for the Siemens EDA Questa Formal Verification tool.

  • Formal Verification for DO-254 (and other Safety-Critical) Designs

    DO-254 defines a process that hardware vendors must follow to get their hardware certified for use in avionics. All in-flight hardware (i.e., PLD, FPGA or ASIC designs) must comply with DO-254. This document focuses on the issue of advanced verification and tool assessment for DO-254, specifically for the Siemens EDA Questa Formal Verification tool.

  • Understanding Formal Methods for Use in DO-254 Programs

    This paper seeks to take the mystery out of the use of formal methods for hardware verification. We will first explain formal methods as clearly and concisely as possible. We will then look at the state of the industry and the changes over the last decade or so that have enabled the widespread use of formal methods for hardware verification. Finally, we will bring this information together and provide recommendations for using formal methods on a DO- 254 project.

  • Understanding Formal Methods for Use in DO-254 Programs

    This paper seeks to take the mystery out of the use of formal methods for hardware verification. In this discussion, we will first explain formal methods as clearly and concisely as possible.

  • Leveraging Advancements in UPF 3.1 for Effective Design and Verification

    In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

  • Part I: Introduction to PCIe® Gen 6

    In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe® 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

  • Introduction to UVM

    This session gives an overview of UVM, the motivation and benefits, and technical highlights.

  • Introduction to UVM | Japanese

  • Introduction to UVM

  • UVM "Hello World" | Japanese

  • UVM "Hello World"

    This session walks through a short, simple example to get you started with UVM.

  • UVM "Hello World"

  • Connecting Env to DUT

  • Connecting Env to DUT | Japanese