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Comprehensive Memory Modeling - DDR Questa Verification IP
Webinar - Sep 15, 2020 by Kamlesh Mulchandani
In this session, you will learn how IP, SoC and FPGA customers successfully perform memory verification amidst growing protocol complexity.
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Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success
Webinar - Sep 01, 2020 by Jin Hou
In this session we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.
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Stimulating Simulating: UVM Transactions
Webinar - Aug 26, 2020 by Chris Spear
In this session, you will learn how to create classes for UVM transactions, also known as sequence items. You will also be shown how to add new functionality to a transaction, by extending the class and much more.
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Verilog Basics for SystemVerilog Constrained Random Verification
Webinar - Aug 18, 2020 by Dave Rich
In this session we will review two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values.
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Formal Is The “New Normal” - Deploy These FV Apps In Your Next Project
Article - Jul 19, 2020 by Ajeetha Kumari, Hemamalini Sundaram, and Darshan Ballari, VerifWorks, LLC and CVC Pvt., Ltd.
Formal verification is now pervasive in many chip design verification projects. Key to this widespread adoption is the availability of automated “apps” that makes it easy to deploy Formal in hitherto simulation-only projects. We at VerifWorks have a long history of formal deployment at many design houses and have seen the challenges engineers face while adopting the same. We have also trained hundreds of engineers to use Formal with ABV (Assertion-Based Verification) through CVC.
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Understanding the SVA Engine Using the Fork-Join Model
Article - Jul 19, 2020 by Ben Cohen
SVA ( SystemVerilog Assertions ) is a powerful short-handed assertion language with many constructs; it is built as an integral part of SystemVerilog but with a specific syntax and sets of rules. Unlike a scoreboard that tends to focus on a model implementation that mimics the DUT, SVA addresses the requirements; that brings out a better understanding of the requirements, along with its weaknesses for lack of definitions.
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Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC
Article - Jul 19, 2020 by Kiran Malvi, Priyanka Gharat, Past Dean Prof Sastry Puranapanda - Silicon Interfaces®
This article focuses mostly on the vertical reuse of the test intent from IP-block to Sub-System and study of reusability from Sub-system to SoC level. The example taken to demonstrate vertical reusability is a single master and slave SPI Core IP configuration. A UVM layered testbench is wrapped around the design to verify and validate proper functioning of SPI Core IP.
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PCIe® Simulation Speed-Up with PLDA PCIe® Controller for DMA Application
Article - Jul 19, 2020 by Akshay Sarup
PCI Express® (PCIe®) is a dominant technology for hardware applications requiring high-speed connectivity between networking, storage, FPGA, and GPGPU boards to servers and desktop systems. It is a robust technology that has evolved over decades to keep up with advancements in throughput and speed for I/O connectivity for computing requirements.
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Extending SoC Design Verification Methods for RISC-V Processor DV
Article - Jul 19, 2020 by Larry Lapides
As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of ‘known good processor IP’ based on the quality expectations associated with IP providers such as Arm or MIPS Technologies.
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Addressing VHDL Verification Challenges with OSVVM
Article - Jul 19, 2020 by Jim Lewis
Most people don't think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM.
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Effective Validation Method of Safety Mechanism Compliant with ISO 26262
Article - Jul 19, 2020 by Toshiyuki Hamatani - Verification Technology, Inc.
The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations, which will cause a significant increase in time and cost compared to consumer LSIs.
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When Are You Done Running CDC?
Webinar - Jul 16, 2020 by Chris Giles
In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.
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When Are You Done Running CDC?
Resource (Slides) - Jul 16, 2020 by Chris Giles
In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.
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Get Your Bits Together: SystemVerilog Structures and Packages
Webinar - Jul 14, 2020 by Chris Spear
In this session, you will learn best practices for structures and packages in the SystemVerilog language and how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused.
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Simplifying Questa Usage and Deployment with Qrun
Webinar - Jul 09, 2020 by Tom Kiley
In this session, you will learn how to reduce the complexity of compiling, optimizing, elaborating, and simulating your design. Qrun encapsulates the details of the QuestaSim tool invocation. Users commonly write scripts or makefiles to encapsulate these steps.
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Introduction to Visualizer for the VHDL Users
Webinar - Jun 30, 2020 by Rich Edelman
This session will introduce the Visualizer Debug Environment for VHDL and UVM.
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Introduction to Visualizer for the Verilog Users
Webinar - Jun 16, 2020 by Rich Edelman
This session will introduce the Visualizer Debug Environment for Verilog and UVM.
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Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance
Session - Jun 11, 2020 by Jacob Wiltgen
In this session, you will learn about a powerful combination of Mentor’s functional verification and functional safety products together with Siemens’ lifecycle management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.
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Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
Webinar - Jun 11, 2020 by Chris Giles
In this session, you will learn the full scope of synchronization issues and how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market.
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Taking SystemVerilog Arrays to the Next Dimension
Webinar - Jun 05, 2020 by Chris Spear
In this session, you will learn the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. As a result, your testbench code will be easier to understand and reuse, run faster, and consume less memory.
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Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal
Webinar - Jun 04, 2020 by Mark Eslinger
In this session, you will learn how formal analysis works, and you can create an effective "formal testbench" with very basic, easy-to-write properties.
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Deadlock Verification For Dummies - The Easy Way Using SVA and Formal
Webinar - Jun 02, 2020 by Mark Eslinger
In this session we will show how combining the above concepts using normal SVA liveness properties allows for RTL engineers to achieve the benefit of formal deadlock analysis without the iterative component or learning a non-standard assertion language. Deadlock verification for dummies!
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Better UVM Debug
Resource (Tarball) - Jun 02, 2020 by
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Better UVM Debug with Visualizer
Webinar - Jun 02, 2020 by Rich Edelman
In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.
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Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP
Webinar - May 28, 2020 by Munish Goyal
In this session, you will learn how Questa Verification IP is architected for ease of use and how the library gives you everything you need to verify standard protocols in your UVM environment.