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1771 Results
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I Didn't Know Visualizer Could Do that
Resource (Slides) - Feb 05, 2021 by Rich Edelman
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ISO 26262 Creating an Optimal Safety Architecture
Resource (Slides) - Feb 02, 2021 by Jacob Wiltgen
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ISO 26262 Creating an Optimal Safety Architecture
Session - Feb 02, 2021 by Jacob Wiltgen
In this session you will gain an understanding of the core challenges defining an optimal safety architecture.
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Mil/Aero Analysis Functional Verification Study - 2020
Resource (Technical Paper) - Jan 20, 2021 by Harry Foster
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Mathworks Integration
Resource (Slides) - Dec 29, 2020 by Bob Oden
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Mathworks Integration
Session - Dec 29, 2020 by Bob Oden
In this session you will learn how the UVMF code generator can automatically integrate blocks created using Mathworks® products.
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Embedded Software Debug Using Codelink and Visualizer
Webinar - Dec 08, 2020 by Tomasz Piekarz
In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.
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Visualizer Coverage: Debug and Visualize All Your Coverage
Webinar - Nov 19, 2020 by Athira Panicker
In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.
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I’m Excited About Formal…My Journey From Skeptic to Believer
Resource (Slides) - Nov 09, 2020 by
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ISO 26262 Fault Campaign Management
Resource (Slides) - Oct 29, 2020 by Jacob Wiltgen
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ISO 26262 Fault Campaign Management
Session - Oct 29, 2020 by Jacob Wiltgen
In this session you will gain an understanding of the core challenges executing an ISO 26262 Fault Campaign and a methodology to ensure maximum efficiency.
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Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
Webinar - Oct 27, 2020 by Jason Polychronopoulos
This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.
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Quantifying FPGA Verification Effectiveness
Article - Oct 26, 2020 by Harry Foster
The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021 [1] . The FPGA portion of the semiconductor market is valued at about $5 billion [2] . The FPGA semiconductor market is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4% during this forecast period.
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Arasan MIPI® CSI-2-RX IP Verification Using Questa Verification IPs
Article - Oct 26, 2020 by Vikas Sharma - Siemens EDA
This article describes the verification process of the ARASAN MIPI® CSI-2-RX IP core using Questa Verification IPs.
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Memory Softmodels - The Foundation of Validation Accuracy
Article - Oct 26, 2020 by Ridham Kothari - Siemens EDA
As always, we must continue to reduce the time-to-market of SoCs and complex systems. An FPGA prototype implementation of these systems can be used as a basis for early software or firmware development, hardware-software co-verification and system validation, and all this can be achieved before actual silicon is available.
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Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver
Article - Oct 26, 2020 by Karthik Bandaru, Priyanka Gharat, and Sastry Puranapanda - Silicon Interfaces®
The efforts to apply constrained randomization to create test cases is based on the developer or verification engineer’s perception of what test vectors are required and can easily lead to hidden bugs being overlooked. Traditionally, the coverage goals would have been reached by writing more test cases with unpredictable schedules, often impacting time-to-market goals. Functional coverage defines critical states and constrained randomization tests those states in unpredictable ways.
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Unified Approach to Verify Complex FSM
Article - Oct 26, 2020 by Milan Patel - eInfochips, LTD (an Arrow Company)
The purpose of this article is to share a strategy on how to verify any simple or complex FSM in an organized, robust, manageable, and efficient way. To verify such FSMs thoroughly we need random scenarios that cover all the possible state transition conditions, corner and boundary conditions, and relevant functional behavior. For that, we require a strong base entity that helps to generate random scenarios to cover all FSM entry-exit conditions and erroneous scenarios easily.
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RISC-V Design Verification Strategy
Article - Oct 26, 2020 by Dr. Mike Bartley
As the RISC-V architecture becomes increasingly popular, it is being adopted across a diverse range of products. From the development of in-house cores with specialized instructions, to functionally safe SoCs and security processors for a variety of verticals – RISC-V adoption brings several verification challenges that are discussed in this article, along with potential approaches and solutions.
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Reducing Area & Power Consumption with Formal-based ‘X’ Verification
Webinar - Oct 15, 2020 by Ping Yeung
In this session we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process.
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Functional Verification Study - 2020
Session - Oct 13, 2020 by Harry Foster
In this session, Harry Foster highlights the key findings from the 2020 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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FPGA Functional Verification Trend Report - 2020
Resource (Slides) - Oct 13, 2020 by Harry Foster
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Stimulating Simulating 2: UVM Sequences
Webinar - Oct 08, 2020 by Chris Spear
In this session, you will learn more about UVM Sequences; creating classes, transactions flow and virtual sequences. In addition, Chris will share best practices with UVM sequence classes.
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Ethernet Questa VIP - Boost Productivity & Faster Sign-Offs
Webinar - Oct 06, 2020 by Shubhankar Deshmukh
In this session, we will demonstrate how Ethernet QVIP's comprehensive portfolio, unencrypted utilities and seamless integration is enabling users to boost productivity and quickly start meaningful verification resulting in faster sign-offs.
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ISO 26262 Bottoms-Up Safety Analysis
Resource (Slides) - Sep 29, 2020 by Jacob Wiltgen
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ISO 26262 Bottoms-Up Safety Analysis
Session - Sep 29, 2020 by Jacob Wiltgen
In this session you will gain an understanding of the core challenges performing safety analysis in today’s complex IP and IC architectures.