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Questa Visualizer Adds Coverage Analysis to the Platform
Article - Sep 01, 2021 by Yara Esam - Siemens EDA
Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.
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Verifying a DDR5 Memory Subsystem
Article - Sep 01, 2021 by Kamlesh Mulchandani
The latest technologies and applications often demand more speed and performance. With the advancement in technologies such as multi-core CPUs and GPUs, the need for faster data processing is becoming a bottleneck for system performance. Applications such as Machine Learning and Data Centers rely upon high performance and lower latency. These applications need a memory that can offer high speed, better performance, high density, lower latency, and data integrity.
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Expediting Simulation Turn-around Time with Incremental Build Flow
Article - Sep 01, 2021 by Neil Johnson
Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use to constantly validate progress. Whether the result is a failed compile, passing simulation or anything in between, the sooner you get that result, the sooner you get to the next step and closer you get to your ultimate objective: passing silicon.
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Standards Participation at Siemens EDA
Article - Sep 01, 2021 by Dave Rich
All of us are involved with standards every day whether we realize it or not. From the day we are born, we interact with standards. In the US, a baby receives a standardized health assessment score called Apgar after 1 minute. You are weighed and measured to standards. You wear clothes sized to standards. Eventually, you learn to read and write according to some culturally accepted standards.
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IP Security: Keys to Early Identification of Security Vulnerabilities
Webinar - Aug 27, 2021 by John Hallman
In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.
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UVM Connect 2.3 Primer
Resource (Reference Documentation) - Aug 25, 2021 by John Stickley
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RDC Overview & Questa RDC Methodology
Webinar - Aug 21, 2021 by Atul Sharma
In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.
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RDC Overview & Questa RDC Methodology
Resource (Slides Download) - Aug 21, 2021 by Atul Sharma
In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.
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Should I Kill My Formal Run? Part 1: Formal Run is In-Progress
Webinar - Aug 20, 2021 by Dr. Jeremy Levitt
In this session we will show you the information you can use to decide whether to continue or stop the formal job such as how to monitor the formal engines’ “health” in real time and why a given property analysis might be getting stuck.
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Exploration into Safety Analysis Techniques That Optimize the Safety Workflow
Webinar - Aug 13, 2021 by Ann Keffer
In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.
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UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
Webinar - Aug 05, 2021 by Pedram Riahi - Raytheon
This session is a customer presentation on his experience using the UVMF and Mathworks® integration in block, subsystem, and chip level simulations.
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Managing Requirements in a Functional Safety Environment
Webinar - Jul 29, 2021 by Thorsten Stahlberg - Siemens EDA
In this session, you will learn that Requirements Management in a "Functional Safety" environment can be very challenging. With Polarion ALM you have a comprehensive solution at hand that fully supports you in successfully managing not only the pure requirements themselves but also all related processes.
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Using Formal Verification in Daily Work
Webinar - Jul 29, 2021 by Dr. Abdelouahab Ayari - Siemens EDA
In this session, we will describe some typical formal applications and how the formal results can be integrated with other verification results.
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Digital Functional Verification for Safety-Critical Automotive Applications
Webinar - Jul 29, 2021 by Michael Bierl - Siemens EDA
In this session, you will be shown a coverage driven verification flow based on the Questa platform. You will also learn how a web-based platform helps to finalize the project successfully even in teams spread over multiple locations.
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CDC Verification: Beyond Structural Analysis
Webinar - Jul 29, 2021 by Mark Handover
In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.
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Mitigating the Effects of Random Hardware Faults
Webinar - Jul 29, 2021 by Dirk Hansen
Random faults cannot be prevented so the goal there is to sufficiently tolerate them. With random faults you are really just trying to make sure that the product will fail safely when inevitably one of these random hardware faults occurs. In this session we will outline approaches on how to tackle systematic as well as random faults.
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AMS Functional Verification for Safety-Critical Automotive Applications
Webinar - Jul 29, 2021 by Sumit Vishwakarma
In this session, you will learn how Siemens EDA Symphony platform addresses today's nanometer mixed signal verification challenges for safety-critical automotive applications.
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A Path to Develop Safe ICs - Part 2
Webinar - Jul 29, 2021 by Stephanie Dournelle, Paul Williams - Siemens EDA
In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.
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A Path to Develop Safe ICs - Part 1
Webinar - Jul 29, 2021 by Stephanie Dournelle - Siemens EDA
In this session, you will learn that Siemens EDA helps customers adapt to the required development flows, develop safety collateral for their designs, and mitigate the risk of product failure in safety critical applications.
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Extending the Role of Test and In-System Test to Meet Automotive Safety and Security Requirements
Webinar - Jul 29, 2021 by Lee Harrison
In this session, we will show how Design For Test is expanding from its traditional role into one that includes the management of the entire silicon lifecycle, to become Silicon Lifecycle Solutions. Ensuring that ICs work safely as expected and are secure throughout their operational life.
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Hardware-Accelerated & Software-Driven Verification
Webinar - Jul 29, 2021 by Ajay Sharma
In this session we will talk about ease of adopting Emulation and various ways of using the powerful Apps that bring in software to improve accuracy of verification process.
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Automotive SOTIF Compliance for Arm with PAVE360
Webinar - Jul 29, 2021 by Antonio Priore - Arm, Joe Dailey - Siemens, Tapan Vikas - Siemens EDA
In this session, we will explain Safety Of The Intended Function (SOTIF) and demonstrate techniques to prove systems.
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Are Random Hardware Faults Common?
Webinar - Jul 29, 2021 by Dirk Hansen
In this session, you will be given an introduction of solutions to analysis failure modes resulting from random hardware faults. These can guide the user to unsafe areas of the design where safety mechanisms need to be inserted.
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Traceability for Automotive Standards Compliance
Webinar - Jul 29, 2021 by Darron May
In this session, you will learn how the combination of Siemens Polarion ALM Requirements Management and Questa Verification Management solve the lifecycle management and traceability requirements for Automotive projects.
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Creating a Fast and Productive USB4 Verification Environment
Resource (Slides Download) - Jul 29, 2021 by Didan Francis
Developing a testbench with complex Verification IP components is a monumental task taking up many weeks and multiple iterations in the verification cycle of a SoC development project. QVIP Configurator is a Graphical User Interface (GUI) based tool aimed at providing a jump start for building a complete ready-to-use testbench for Questa Verification IP with the ability to re-use components into an existing testbench.