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1979 Results

  • Reporting

  • Reporting | Japanese

  • Reporting

    This session explains message reporting in UVM, and shows simple ways in which reporting can be customized.

  • UVM Basics

    UVM Basics will raise a user's level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.

  • Architecting a UVM Testbench

    This session covers the basic architecture of a UVM testbench, including the introduction of the Agent/UVC component.

  • Architecting a UVM Testbench

  • Understanding the Factory and Configuration

  • Understanding the Factory and Configuration

    This session shows how tests can use the factory to control the type of components that get instantiated in a UVM environment.

  • Modeling Transactions

    This session outlines the methods needed in the design of a sequence item (a.k.a. “transaction") for use in UVM.

  • Modeling Transactions

  • How TLM Works

  • How TLM Works

    This session discusses the use of TLM interfaces in UVM to facilitate the creation of modular, hierarchical components.

  • The Proper Care and Feeding of Sequences

    This session covers the creation and execution of sequences, including the interaction of the sequence and driver.

  • The Proper Care and Feeding of Sequences

  • Layered Sequences

  • Layered Sequences

    This session shows how to create a virtual sequence, which controls the execution of other sequences and how to model layered protocols.

  • Setting Up the Register Layer

    This session introduces the UVM Register Layer, showing you how to create register models that reflect the operation of the hardware registers in your DUT.

  • Writing and Managing Tests

    This session shows how to create a set of tests derived from a base test that defines the default setup of your environment, including how to invoke specific tests from the command line.

  • Writing and Managing Tests

  • Setting Up the Register Layer

  • Using the Register Layer

    This session discusses the various methods that a test can use to access the register model, including both “front-door” and “back-door” accesses.

  • Using the Register Layer

    Using the Register Layer will also show how to create register-bases stimulus sequences to simplify the API.

  • Register-Based Testing

    This session shows how to round out your register-based test environment with register-level scoreboards and functional coverage.

  • Register-Based Testing

  • The Three Witches Preventing Glitch Nightmares on CDC Paths

    At the RTL, we focus on identifying the clock domains and CDC paths by recognizing the CDC structures and schemes. At the gate-level, CDC paths with multiplexer or combinational logic are often prone to glitch defects that can be introduced during the synthesis, timing, and power optimization process. If CDC verification is only done at RTL, such glitch defects can easily be missed and lead to costly post-silicon chip failure.