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2075 Results

  • Continuous Integration (CI) / DevSecOps

    Modern systems and products rely on complex microelectronic components now more than ever to monitor, control and process critical information. Due to their importance in the system or product, an exploit of these devices may result in a risk to personal safety, financial loss, exposure of personal information, and operation failure. Functional verification of microelectronic devices requires thorough methods and verifying that the ICs in the system are free of these exploits requires even more.

  • Integrating the Value of Questa Design Solutions Into Your Continuous Integration (CI) Development Flow

    In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution.

  • Whoops There Goes Another Config

    This is all made up. Except the true parts. It’s a murder mystery. Someone “murdered” my config setting – but I’m getting ahead of the story. We’re verification engineers, and our testbench is running just fine, doing the things it does, but the system is running a bit slower than our System Architects predicted.

  • Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project

    In this article, we will discuss the Display Data Bus of ARINC-708. The bus plays a critical role in terms of the pilot’s point of view. It requires a bi-phase Manchester encoding and decoding. For both Manchester coding and the bus protocol, some examples of possible error types are considered.

  • Mitigating System Failure Risks by verifying the Safeness of SafeSPI sub-module for the Automotive Industry

    This article outlines a systematic approach to attain safety objectives and create a conducive environment for achieving them. It includes a comprehensive inventory of alarms, faults, and their corresponding categories, all presented in a step-by-step format.

  • Decoding LLM Hallucinations: Insights and Taming them for EDA Applications

    In an earlier blog , I explained that LLM will learn much faster than humans and there are many possible applications in verification. Two months later, the latest iteration of ChatGPT has been passing many harder exams with flying colors. This has ignited many people’s interest in applying LLMs in more domains including EDA. However, the immediate future may not be as rosy as we might have thought.

  • Driving Deterministic, Efficient Execution with Continuous Integration Flows

    Designer focused tools are proven solutions that help you detect issues as early as possible in the design cycle; reducing costs, and driving predictable schedule execution. Using these solutions in a continuous integration environment -- where design quality is checked at every code check in and at other scheduled intervals -- product teams improve efficiency across the board. Additionally, this directly helps designers and the consumers other their IP by improving the quality of their code.

  • Functional Verification on Cloud: Opportunity and Challenge

    Cloud's dramatic growth is driven by hopes for better throughput, easier workload management, and lower costs. However, you may be asking yourself, " Really? Can renting compute and data storage be a better value than my on-premises data center? ” We will share some of our insights gained working with verification teams to scale projects to many 10's of thousands of simulations run on cloud.

  • Formal Model Checking Made Easy

    In this session anyone who is familiar with VHDL, Verilog, or SystemVerilog, and general verification practices, can learn the basics of formal. You will learn the basics of properties, how you can apply property checking to finding difficult corner case bugs, and easy-to-follow steps for verifying interfaces and other common design structures, as well as general design exploration.

  • Continuous Integration (CI) / DevSecOps

    Siemens' OneSpin Trust and Security tools and apps have technologies built upon world-class formal engines, and provide quantitative data verification results desired in emerging cybersecurity standards. In this presentation we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking to perform security verification in your IC.

  • When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered

    You may have been told many different things about what AI/ML can do in the area of functional verification, but this presentation will give you the real story. Beginning with an overview of what AI/ML actually means and what is actually available today, we will share how we are incorporating this exciting technology across our product portfolio.

  • Using Formal Technology for Secure IP Integration

  • Update on Formal-based Trust and Security Verification Flows

  • Securing RISC-V Military Projects

  • TSS SoC Sign-Off Methodology: Quality & Productivity Gains

  • Formal Verification of Security Properties

  • OneSpin EC-FPGA: Evolution and Updates

    In this session, you will learn how OneSpin EC-FPGA accelerates the design flow and identifies bugs before they escape by enabling aggressive optimization usage.

  • Siemens Government Technologies and Microelectronics Assurance

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

    This session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity, inspired by the collective feedback gathered from verification teams over many years.

  • Integrating the Value of Questa Design Solutions Into Your Continuous Integration (CI) Development Flow

    In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the industry leader for Verification IP. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • Revolutionizing RTL Design: Unveiling the Latest Updates and Roadmap of the Questa Simulation Platform

    During this session we will unveil our latest Questa Simulation platform updates, with a behind-the-scenes look at our strategic investments in expanding functionality, enhancing performance, and delivering more intuitive debug capabilities.

  • Transactional Assertions - Where representation influences thinking

    In this session, you will learn about more about transactional assertions.

  • GapFree - Where all pieces come together

    In this session, you will learn how OneSpin joining Siemens EDA creates a compelling combination by providing a comprehensive, best-in-class, accessible Formal solution.

  • Break the RISC-V customization barrier with Processor Formal Verification

    In this session, you will learn the challenges of processor verification and how the RISC-V community recognizes the need for stronger verification.