Verification Academy

Topic	Replies	Views	Activity
Infinite delay assertion SystemVerilog assertion	7	81	July 2, 2025
Localparam causes wrong time delay SystemVerilog	2	39	July 2, 2025
Synthesizable verilog code SystemVerilog	3	35	July 2, 2025
Illegal assignment mailbox error SystemVerilog	6	50	July 2, 2025
Why do compare need to arguments, specially why second arguments of uvm_comparer comparer UVM UVM	4	41	July 2, 2025
Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts UVM UVM	1	56	July 2, 2025
Fork join none/any? SystemVerilog SystemVerilog , disable-fork , fork-join	8	96	July 1, 2025
Streaming unpacked structure SystemVerilog SystemVerilog	1	25	July 1, 2025
Time not progressing when simulate UVM+UVMC+SystemC UVM SystemC-UVMConnect , UVMC	3	39	June 30, 2025
Confusion regarding range within inside operator SystemVerilog SystemVerilog , Constraint-random-verification , constraint-randomization , inside	3	41	June 30, 2025
Module based coverage vs class based coverage UVM functional-coverage , assertion-coverage	1	31	June 30, 2025
Parameterized interface UVM UVM	3	131	June 30, 2025
Fork join question if we need to disable fork in some condition SystemVerilog	10	69	June 30, 2025
Single uvm_analysis_port with multiple sequence items UVM UVM-TLM-Analysis-port	1	37	June 30, 2025
Constraint for two dimensional array odd numbers in ascending order SystemVerilog constraint	3	55	June 29, 2025
Stop counting of a thread using fork join SystemVerilog Verilog	0	30	June 29, 2025
Type cast error for uvm config db UVM	6	39	June 29, 2025
Different ways of writing Test Sequences UVM	1	42	June 29, 2025
Driving internal module in testbench SystemVerilog simulation	1	40	June 26, 2025
TLM PORTS how it giving the access of other class TASK with other class handle UVM UVM	1	36	June 26, 2025
UVM backdoor register access without register names in RTL but only fields are present UVM regmodel	0	31	June 26, 2025
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM UVM , uvm_reg_bit_bash	5	2178	June 26, 2025
SV cross coverage with 'intersect' keyword SystemVerilog Coverage , cross-coverage-bins	6	40	June 26, 2025
Why final phase is top to bottom? UVM UVM	1	42	June 25, 2025
Sample level triggered signal Coverage Coverage	6	42	June 25, 2025
Making a generic adapter for different interfaces specific SystemVerilog SystemVerilog , Interfaces	3	29	June 24, 2025
UVMF parameters UVM UVMF	3	141	June 24, 2025
Parametrized classes UVM	3	23	June 23, 2025
UVM_FATAL @ 0: reporter@@seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq UVM UVM	2	35	June 23, 2025
Working of sequence method 'matched' SystemVerilog SystemVerilog , SVA , concurrent-assertion , sequence-matched	1	72	June 21, 2025