Could anyone explain the difference between the sequences mentioned below ? What does the 1 and 0 exactly mean here? How can I use this concept in writing sequences?
seq1: a ##1 1 ##1 b
seq2: a ##1 0 ##1 b
A SystemVerilog sequence is a temporal ordering of boolean expressions where each expression must be true (non-zero) at a particular clock cycle. The constant expression 1 is always true, while 0 is always false.
seq1 is the same as a ##2 b. Using the constant 1 makes sense when you want to connect a statement in the middle of a sequence a ##1 (1, lval = addr) ##1 b == lval
Having a Boolean expression that is always false doesn’t make much sense. I can’t think of any practical use for it, but perhaps there’s something out there.
Hi Dave,
One application to use hard zero is for clock gating scenarios ( edalink )
The sequence prior to 0 ideally shouldn’t match. It it does then fail action block should execute.
Although as Ben confirmed it’s illegal from strict LRM perspective ( as it makes the sequence degenerate ), there are alternatives for it ( Eg: not( 1 ) / !( 1 ) )
A 3rd possibility would be declaring a 1-bit variable bit hard_zero which is never assigned ( remains at default 0 ) and is used as seq_expression ( causing the assertion to always fail )