There are cases where I am glad that the tool doesn’t throw a compilation error for hard zero.
Intention :: Once signal ip_en ( clocked on sys_clk ) is asserted , ’ ip_clk ’ should not toggle .
( Ben suggests to use classic SV task for such scenarios )
ip_clk_disable:assert property( @(posedge sys_clk) ip_en ##1 1 |=> @(ip_clk) 0 ) else `uvm_error( ... )
Since a tool may choose to exercise certain sections of the LRM while ignoring certain sections, I meant to ask from LRM perspective should SVA ‘hard_zero’ be treated as degenerate sequence
If yes, this would also mean that ‘ip_clk_disable’ is illegal as well and wouldn’t compile.