Requesting clarity on intermediate signals in the sequences

Hi Dave,

One application to use hard zero is for clock gating scenarios ( edalink )

The sequence prior to 0 ideally shouldn’t match. It it does then fail action block should execute.

Although as Ben confirmed it’s illegal from strict LRM perspective ( as it makes the sequence degenerate ), there are alternatives for it ( Eg: not( 1 ) / !( 1 ) )

A 3rd possibility would be declaring a 1-bit variable bit hard_zero which is never assigned ( remains at default 0 ) and is used as seq_expression ( causing the assertion to always fail )