Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	263	September 13, 2023
Write an assertion such that a given 2-bit command can't be equal to 2 more than 4 times within 60 clock cycles SystemVerilog assertion	1	19	May 31, 2024
Declaration of coverpoint for multidimensional array UVM Coverage	1	12	May 31, 2024
Getting symbol while printing enum SystemVerilog SystemVerilog , UVM	1	9	May 31, 2024
How to access a slice with a dynamic value in SystemVerilog? SystemVerilog	4	28	May 31, 2024
How to find a particular field in a register using RAL and set that for UVM_NO_CHECK UVM UVM	1	11	May 30, 2024
Sampling query when merging different protocols into one single covergroup Coverage	4	124	May 30, 2024
Forever loop inside for loop and using hierarchical access using variable SystemVerilog SystemVerilog , UVM	4	22	May 30, 2024
Creating a seq in another seq UVM	1	20	May 30, 2024
Cannot # delay at ps precision SystemVerilog	1	16	May 30, 2024
FIFO module assertion SystemVerilog SystemVerilog , SVA , system-verilog-assertion-SVA	1	16	May 30, 2024
Including same file in 2 different packages SystemVerilog SystemVerilog , Package	1	19	May 29, 2024
Ambiguous comment in 11.6.1 Rules for expression bit lengths SystemVerilog SystemVerilog , LRM	4	24	May 29, 2024
Demote UVM_ERROR UVM	4	30	May 29, 2024
UVMC installation failed UVM	1	21	May 28, 2024
The way how threading works in assertions SystemVerilog SystemVerilog , SVA-Assertion , formal-property-verification	8	1878	June 8, 2022
Regarding Macro substitution SystemVerilog SystemVerilog , macros , macro-substitution	1	23	May 28, 2024
When to use "int" and "integer"? SystemVerilog SystemVerilog	7	23012	May 28, 2024
UVM_FATAL "attempted to drop objection count below zero" UVM UVM , UVM-phases , Related-to-UVM-phases	1	16	May 28, 2024
Printing RAL MODEL UVM UVM	6	5271	May 28, 2024
Whats the necessity of null bytes in AXI4 Stream Protocol UVM UVM , AXI4-Stream	2	1799	May 28, 2024
System verilog, Constraint SystemVerilog constraint-randomization	2	77	May 28, 2024
Uvm ral - explicit prediction UVM Systemverilog-UVM-RAL	2	25	May 27, 2024
Protect a constraint SystemVerilog	3	49	May 25, 2024
Uvm_test running instead of mytest! UVM uvm_test	1	45	May 25, 2024
Self registering interface UVM	1	32	May 24, 2024
How to use macros in for loop in SV class (NOT A MODULE)? SystemVerilog SystemVerilog	1	31	May 24, 2024
How to add uvm_subscriber in UVMF? UVM	0	28	May 24, 2024
Bind - elab error SystemVerilog bind , systemverilog-ASSERTION-bind	1	32	May 24, 2024
Fork-join_none odd printout behavior SystemVerilog SystemVerilog	1	44	May 24, 2024