Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	768	September 13, 2023
Output observation for $dist_exponential SystemVerilog SystemVerilog , dist_exponential , Distribution-Function	0	2	June 9, 2026
UVM Driver Communication: get_next_item()/item_done() vs get()/put() — Which is Preferred in Industry? UVM UVM	0	3	June 9, 2026
UVM_SEQ_ARB_WEIGHTED Arbitration: How Does It Work and When Should It Be Used? UVM UVM	1	13	June 8, 2026
Why does UVM need both wait_for_grant() and wait_for_item_done()? UVM UVM	3	36	June 8, 2026
UVM Sequencer Arbitration: Is Sequence Priority Used During Queue Insertion or During Grant Selection? UVM UVM	3	19	June 8, 2026
vmm1.2.2b source tar Downloads	0	8	June 8, 2026
Understand the Difference between UVM_SEQ_ARB_FIFO and UVM_SEQ_ARB_STRICT_FIFO UVM	3	28	June 5, 2026
Use of lock() method UVM	1	16	June 5, 2026
Queries on Randomization SystemVerilog constraint-randomization , solve-before	1	22	June 4, 2026
Understanding Array Reduction methods SystemVerilog constraint-arraysum , array-reduction-methods	4	33	June 4, 2026
For understanding factory usage UVM UVM , set_type_override , factory , Polymorhphism	6	1608	June 3, 2026
Why Is Scoreboard Kept Separate from Agent in UVM? UVM UVM	2	52	June 3, 2026
Understanding the Real Difference Between uvm_resource_db and uvm_config_db UVM UVM	2	30	June 2, 2026
Router scoreboard implementation SystemVerilog UVM , scoreboard	0	33	May 29, 2026
Why Did UVM Creators Make Separate Classes for uvm_transaction and uvm_sequence_item? UVM UVM	1	41	May 26, 2026
repeat vs for loop control variable SystemVerilog	1	39	May 26, 2026
Confusion About uvm_void in UVM Hierarchy UVM UVM	3	48	May 26, 2026
Use case of uvm_void UVM	1	33	May 26, 2026
Are class object handles passed by reference when used are class method arguments? SystemVerilog SystemVerilog	5	1388	May 26, 2026
Advantage of $future_gclk over $past in FV SystemVerilog Coverage , assertion , System-Verilog , SVA , Formal-Verification , FV	0	22	May 25, 2026
Calculating probability for solve x,y before z SystemVerilog SystemVerilog , constraint-randomization , randomization , solve-before	4	48	May 23, 2026
Unable to use MINGW's G++ to compile C++ code with DPI-C Export. SystemVerilog SystemVerilog , dpi-c , export-DPI-C	2	21	May 18, 2026
Constraint SystemVerilog SystemVerilog	25	6565	May 17, 2026
Asynchronous reset assertion SystemVerilog SystemVerilog , assertion , reset	14	8913	May 13, 2026
Expression bit-length and Associativity SystemVerilog SystemVerilog , LRM-Size-Casting	5	72	May 11, 2026
[SVA Question] Signal 'b' has to toggle only once within 10cycle window of signal 'a' after 'a' is asserted SystemVerilog assertion , SVA , SVA-Assertion	4	85	May 9, 2026
Creating virtual function to get 'uvm_analysis_export' handles UVM	2	58	May 8, 2026
To check that a signal toggles at least once every 20 cycles SystemVerilog assertion , SVA	11	329	May 6, 2026
Assertion property to check for toggle count of a signal between two control signals SystemVerilog SystemVerilog , assertion , System-Verilog	12	1679	May 6, 2026