Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	744	September 13, 2023
Execution of function after it unblocks SystemVerilog uvm_analysis_imp , analysis-port , uvm_analysis_imp_decl , function-as-task , blocking-function	0	4	March 14, 2026
Soft constraints must be followed by an expression SystemVerilog constraint-randomization , soft-constraints , Implication-constraint	6	40	March 14, 2026
Bug (?) in uvm_pool UVM SystemVerilog , UVM , uvm_event_pool	0	10	March 13, 2026
Back door access for uvm_mem UVM UVM	3	1426	March 13, 2026
Race Between Assign and multiple Initial Blocks SystemVerilog	2	26	March 13, 2026
Randomization of req signal in priority arbiter SystemVerilog constraint-randomization , Priority-arbiter	7	122	March 11, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	32	March 10, 2026
Race between procedural Blocks and always block triggering itself SystemVerilog	2	22	March 8, 2026
assertion to detect a specific switch of a signal SystemVerilog assertion	3	35	March 6, 2026
Upward references in bound interfaces SystemVerilog	5	47	March 3, 2026
Ensuring specific uvm_config_db::set always wins UVM UVM , uvm_config_db	0	59	February 24, 2026
SVA on intersect SystemVerilog assertion	5	63	February 24, 2026
Iteration of elements in an array declared as randc SystemVerilog randc	2	48	February 24, 2026
Configuring agent in Active / Passive mode UVM uvm_config_db , activepassive-agent-configuration , uvm_agent , uvm_active_passive_enum	5	131	February 22, 2026
Bind interface for internal DUT forcing UVM UVM	20	5490	February 21, 2026
Default argument dimension & type in SV subroutines SystemVerilog subroutine , SV-Function , SV-Subroutines	1	22	February 21, 2026
SV Assertions practice questions SystemVerilog assertion	0	60	February 21, 2026
Assertion failure using strong property SystemVerilog SVA , Sva-strong , strong-property , fail-action-block	7	77	February 19, 2026
Automation of creating different parameter sets combinations UVM IP-Parameter	1	29	February 18, 2026
SV Assertions using $past() SystemVerilog SystemVerilog , assertion	2	68	February 18, 2026
How to create a SystemVerilog testbench for my ALU's parent circuit? UVM SystemVerilog , UVM	2	41	February 18, 2026
Working of $monitor SystemVerilog monitor , monitor-SV-System-Function	5	38	February 17, 2026
Connection from monitor to driver in reactive agent UVM	1	32	February 16, 2026
Equivalent expression for intersect operator SystemVerilog SVA , Dave-Rich , SVA-intersect , Ben-Cohen , intersect-operator	1	23	February 15, 2026
P_sequencer / m_sequencer UVM UVM	11	36980	February 13, 2026
Formal arguments to properties / sequences SystemVerilog SystemVerilog , SVA , paramterized-properties	1	28	February 13, 2026
A query about push_back and pop_front SystemVerilog SystemVerilog , UVM	10	3974	February 12, 2026
UVM scoreboard interview question UVM UVM , UVM-scoreboard	4	580	February 12, 2026
Calling parent function via super is calling child class function SystemVerilog	4	47	February 12, 2026