How to use macros in for loop in SV class (NOT A MODULE)?

SystemVerilog
1

I am trying to use macros in for loop in SV class (NOT A MODULE), but for loop var is not translated to int, rather passed as string to macro. Is there way to solve this?

// macro define
`define SIGNAL_PATH(NUM_MOD) rtl_top.abc``NUM_MOD``.signal_name

WORKS:
 (`SIGNAL_PATH(0))  //returns rtl_top.abc0.signal_name
 (`SIGNAL_PATH(1)) //returns rtl_top.abc1.signal_name

FAILS:
for (int inst_num=0; inst_num<2; inst_num++) begin
  (`SIGNAL_PATH(i)) //return   rtl_top.abcinst_num.signal_name
end
2 
Found one solution
string get_macro;
for (int inst_num=0; inst_num<2; inst_num++) begin
   get_macro = $sformatf("`SIGNAL_PATH(%0d)", i);
   get_macro;
end
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