System verilog, Constraint

SystemVerilog
1

i tried to write constraint for below question but didn’t get expected result
Question: Write a constraint on a 32-bit variable such that 7 bits are set consecutively and rest of the bits can also have bits set to 1 but consecutive bit set count cannot exceed 4

My code:

class tb;
  rand bit [31:0] a;
   int i=0;

  constraint a_c{if(a[i]==1){
    a[i]==1; a[i+1]==1;a[i+2]==1;a[i+3]==1;a[i+4]==1;a[i+5]==1;a[i+6]==1;a[i+7]==0;}
    else if(a[i]==0){
      a[i+6]!=7'b1111111;}}
endclass

module tb_top;
  tb h;

  initial begin
    h = new();
    //initial begin
    repeat(5) begin
      h.randomize() with {h.a[0]==1;};
      $display("%b", h.a); end
  end
endmodule
2 
class tb;

  rand bit [31:0] a;
  bit[6:0] fixed = 7'h7f;
  rand bit[5:0] len1, len2;
  rand bit [31:0] q1, q2;

constraint a_c{
  len1+len2 == 25;
  foreach(q1[i]){
    	
    if(i<28 && i+4<len1) 
      {q1[i+3],q1[i+2],q1[i+1],q1[i]} != 4'hF;
    if(i>=len1)
     q1[i] == 0;
  }
  foreach(q2[i]){    
    if(i<28 && i+4<len2)
      {q2[i+3],q2[i+2],q2[i+1],q2[i]} != 4'hF;
    if(i>=len2)
     q2[i] == 0;
  }
}
  
  function void post_randomize();
      q2 = q2 << (32-len2);
      a = (q2 | (fixed << len1) | q1);
  endfunction

endclass

module tb_top;
  tb h;
initial begin
  h = new();
  repeat(5) begin
  if(!h.randomize()) $fatal(1, "Randomize Failed");
    $display("len1 = %d,len2 = %d, a= %h", h.len1, h.len2, h.a); 
end
end
endmodule
3

Thank you sabarish

4

can you please explain this? I cant get this

5

//Below logic worked for me to Generate 7 consecutive ones and there are no more than four consecutive 1’s .

module tb();
  
  class simple;
    
    rand bit[31:0]addr;
    rand int value;
    
    constraint c_value{
     
      value inside {[0:25]};
      foreach(addr[i]){
        if(i inside{[value:(value-1+7)]}){
          addr[i] == 1; 
        }else if (i == value-1 || i == (value+7)){
          addr[i] == 0;
        } else if (i>3 && i<27){ 
          //addr[i] == 0 || 1;
          if({addr[i-1], addr[i-2], addr[i-3], addr[i-4]} == 4'b1111){
            addr[i] == 0;
          }
          //addr[i-:3] != 4'b1111;   
        }
      }
      
    }
    
  endclass
          
  initial begin
    
    simple s= new();
    repeat(1) begin
      s.randomize();
      $display("The value = %0d and addr = %0b", s.value, s.addr);
    end
    
  end
  
endmodule
6 

class abc;
  rand bit[31:0] arr;
  rand bit[31:0] val;
  constraint arr_c{
    val inside {[0:12]};
    foreach(arr[i]){
      if(i>=7) arr[i-:4] != '1;

      }      
      arr[6:0] == '1;
        }
    
      //
  
    function void post_randomize(); 
     $display("value of array = %b",arr);
    endfunction   
endclass: abc

module tb;
   abc abc_inst;
  initial begin 
    abc_inst = new();
    repeat(10)
    abc_inst.randomize();

  end
endmodule