I tried to run my test with the +UVM_TESTNAME=mytest plusarg. But uvm_test runs instead and these are the prints I get :
# UVM_INFO @ 0: reporter [RNTST] Running test uvm_test (via factory override for test “mytest”)…
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] End Of Elaboration
# ** Note: (vsim-51106) MVC @ 0 ps: /top/mvc_us_usb_if: Attempt to pause the clock when it is externally driven, this has been ignored
# ** Note: (vsim-51106) MVC @ 0 ps: /top/mvc_usb2_device_if_0: Attempt to pause the clock when it is externally driven, this has been ignored
# ** Note: (vsim-51106) MVC @ 0 ps: /top/mvc_usb2_device_if_1: Attempt to pause the clock when it is externally driven, this has been ignored
# ** Note: (vsim-51106) MVC @ 0 ps: /top/mvc_usb2_device_if_2: Attempt to pause the clock when it is externally driven, this has been ignored
# ** Note: (vsim-51106) MVC @ 0 ps: /top/mvc_usb2_device_if_3: Attempt to pause the clock when it is externally driven, this has been ignored
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.pre_reset’ (id=172) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.reset’ (id=184) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.post_reset’ (id=196) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.pre_configure’ (id=208) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.configure’ (id=220) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.post_configure’ (id=232) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.pre_main’ (id=244) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.main’ (id=256) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.post_main’ (id=268) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.pre_shutdown’ (id=280) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.shutdown’ (id=292) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘common.run’ (id=93) PHASE READY TO END
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1215) @ 0: reporter [PH_READY_TO_END] Phase ‘uvm.uvm_sched.post_shutdown’ (id=304) PHASE READY TO END
I have not provided any overrides for test. Then why is UVM overriding my test and running uvm_test? Where should I start my debug?