Assertion error

SystemVerilog
, , ,
1

Iam Getting error loop_cnt is not matching with cnt value.
Actuaally loop count is not incrementing.

   if(prbs_pgc_cfg_h.run_forever==0)
begin //{
  PRBS_ASSERT83: assert((loop_cnt==cfg_h.cnt) &&
  (exp_row==0) &&
  (exp_col==0) &&
  (t1_exp_ba==0) &&
  (t1_exp_bg==0) &&
  (t2_exp_ba==1) &&
  (t2_exp_bg==0)) else
  `uvm_error(get_type_name(),$sformatf(“%0d,%0d,%0d,%0d,%0d,%0d,%0d - %0d”,loop_cnt,exp_row,exp_col,t1_exp_ba,t1_exp_bg,t2_exp_ba,t2_exp_bg,cfg_h.cnt))
end //}
2

That’s unfortunate news. How could we possibly help you without seeing how loop_cnt and cnt are being set, and when the assertion is executing.

3

Hi Dave,
loop_cnt increments only after a complete read/write cycle finishes, based on these conditions:

  1. After finishing all rows
    When exp_row exceeds max_row and sh_act_done == 1 (second half ACT done), the code resets for the next cycle.

  2. Depending on mode:

    • If rd_loop = 1 (read-only loop mode):

      • You alternate between WR → RD.

      • loop_cnt increments after RD completes (because WR just switches to RD without increment).

    • If rd_loop = 0 (normal mode):

      • You alternate WR ↔ RD (or WR16 ↔ RD16 for LPDDR5).

      • If DM (data mask) is enabled, you also toggle partial write (exp_par_wr).

        • Increment happens after both parity states are done.

      • If DM is disabled, increment happens every full WR/RD cycle.

4

Main thing is what is observed here is in sim.log before the if condition which ever prints are there that iam seeing but after if the condition prints am not seeing in log.
if it enters the if condition loop_cnt will increase.

if(ddrmc6a_pgc_ddr_monitor_h.cmd.first(lcl_idx))  
  begin //{

        do    
  begin //{

            if(`MY_CFG_CENTRAL.glb_cfg.dram_density<64)                    ddrmc6a_pgc_ddr_monitor_h.row[lcl_idx][17]=0;        
`endif         
`uvm_info(get_type_name(),$sformatf(“lcl_idx=%0d, %s”,lcl_idx,ddrmc6a_pgc_ddr_monitor_h.cmd[lcl_idx]),UVM_LOW)          `uvm_info(get_type_name(),$sformatf(“fh_cas_done=%b,fh_pre_done=%b,fh_ref_done=%b,fh_act_done=%b”,fh_cas_done,fh_pre_done,fh_ref_done,fh_act_done),UVM_LOW)          `uvm_info(get_type_name(),$sformatf(“sh_cas_done=%b,sh_pre_done=%b,sh_ref_done=%b,sh_act_done=%b”,sh_cas_done,sh_pre_done,sh_ref_done,sh_act_done),UVM_LOW)          `uvm_info(get_type_name(),$sformatf(“first_time=%0d,loop_cnt=%0d exp_row=%0d,exp_col=%0d,thr1_exp_ba=%0d,thr1_exp_bg=%0d,thr2_exp_ba=%0d,thr2_exp_bg=%0d,exp_par_wr=%b”,first_time,loop_cnt,exp_row,exp_col,thr1_exp_ba,thr1_exp_bg,thr2_exp_ba,thr2_exp_bg,exp_par_wr),UVM_LOW)