Working of uvm_cmdline_processor::get_arg_matches

UVM
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1

Hi Forum,
I notice the following code in uvm_root which looks for certain run-time args

 uvm_cmdline_processor clp;

 // Within constructor of uvm_root it's initialized
 clp = uvm_cmdline_processor::get_inst();

// Function 'm_do_config_settings() is called from uvm_root::build_phase()
function void uvm_root::m_do_config_settings();
  string args[$];

  void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_INT|uvm_set_config_int)=/",args));
  foreach(args[i]) begin
    m_process_config(args[i].substr(20, args[i].len()-1), 1);
  end
  void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_STRING|uvm_set_config_string)=/",args));
  foreach(args[i]) begin
    m_process_config(args[i].substr(23, args[i].len()-1), 0);
  end
  void'(clp.get_arg_matches("/^\\+(UVM_SET_DEFAULT_SEQUENCE|uvm_set_default_sequence)=/", args));
  foreach(args[i]) begin
    m_process_default_sequence(args[i].substr(26, args[i].len()-1));
  end
endfunction

I am not clear on the presence of prefix /^\\+ and suffix / as well as the opening and closing parenthesis within argument to get_arg_matches.

User would provide run-time arg. as +uvm_set_config_int=uvm_test_top.env,test_variable,7.

The actual run-time arg. is not prefixed with /^\\+( or suffixed with )=/ at the end.

Seeking suggestions on it

Thanks

2

uvm_cmdline_processor::get_arg_matches uses extended regular expressions(POSIX ERE)

The enclosing "/string/" means to search the argument for a matching regular expression, whereas "string" would be looking for an argument with an entire exact match.

The ^ symbol indicates that the regular expression must be at the beginning of the argument. In SystemVerilog strings, the backslash \\ is interpreted as a single backslash \ in the actual regular expression. Additionally, the \+ character in POSIX Extended Regular Expressions (ERE) represents a literal plus sign +.

Parentheses are used to group alternatives that match expressions. For instance, (string1|string2) indicates that there must be a match of either string1 or string2. And that must be followed by a = symbol.

2 Likes
3

Thanks Dave. I am currently referring to one of the sublinks along with some additional links

( link1 , link2 , link3 , link4)

Will update this thread in case of any further queries

4

Hi Dave,

Could you please elaborate on the above 3 lines ?

I tried understanding it using the following example

`include "uvm_macros.svh"
import uvm_pkg::*;  
module top;

  string str[$];
  uvm_cmdline_processor clp;

 initial begin
   clp = uvm_cmdline_processor::get_inst();
    
   if( clp.get_arg_matches("+USER_STRING=",str) ) begin:b1       
     $display("+USER_STRING=%0p passed",str);
   end
    else $display("+USER_STRING Not passed"); 

    str.delete();
    
   if( clp.get_arg_matches("/^\\+USER_STRING=/",str) ) begin:b2       
     $display("+USER_STRING=%0p passed",str);
   end
    else $display("+USER_STRING Not passed"); 
 
 end    
endmodule

Assuming run-time arg. has special characters I tried passing it as either (a) or (b)

(a) +USER_STRING=Animal#(elephant) (b) +USER_STRING=Animal\#\(elephant\)

In (a) I observe +USER_STRING='{"+USER_STRING=Animal#(elephant)"} passed for both b1 & b2

In (b) I observe +USER_STRING='{"+USER_STRING=Animal#\(elephant\)"} passed for both b1 & b2

As the display messages are same in both blocks, I don’t see advantage of using b2 over b1.