How SV handles the execution of functions

SystemVerilog
1

So from my understanding, the functions execute in the process of the caller. and the event scheduler schedules events in order.

Now does the processing of these events and eventually the functions happen sequentially or does it allow for parallelism to take place here? is SV and the handling of these events inherently a single threaded process?

So for example if two UVM monitors were to call their TLM port functions during the same active region, are they then always handled in (uncertain but) sequential order? is it hardware / simulator dependent?

Or the second example for extra clarity if we have 2 events, and they both have some function that is being called in them at the same time, then it will execute 1 of the events at random first, and go through and executes the whole call stack of that function.. so multiple functions in a row.. and only when that is all done is when it executes the second event?

2

The procedural statements within a single process execute in a sequential order. Calling a task or function is an integral part of this process, and the statements inside those procedures are also included in this ordering. However, when multiple processes are involved, either due to multiple initial/always blocks or fork/join blocks, the order of statement execution between processes is left undefined.

Software simulators have the liberty to switch between processes at any given moment, whereas hardware simulators can execute processes concurrently on dedicated hardware. Typically, these tools employ a deterministic approach to facilitate debugging, but never depend on it as the ordering of these processes may vary between different versions of the same tool.