Verification Academy

Topic	Replies	Views	Activity
Output observation for $dist_exponential SystemVerilog SystemVerilog , dist_exponential , Distribution-Function	3	43	June 11, 2026
Why Use convert2string() in UVM When We Can Simply Use display()? UVM UVM	1	31	June 10, 2026
Use of lock() method UVM	3	47	June 9, 2026
UVM_SEQ_ARB_WEIGHTED Arbitration: How Does It Work and When Should It Be Used? UVM UVM	1	51	June 8, 2026
Why does UVM need both wait_for_grant() and wait_for_item_done()? UVM UVM	3	53	June 8, 2026
UVM Sequencer Arbitration: Is Sequence Priority Used During Queue Insertion or During Grant Selection? UVM UVM	3	34	June 8, 2026
vmm1.2.2b source tar Downloads	0	18	June 8, 2026
Understand the Difference between UVM_SEQ_ARB_FIFO and UVM_SEQ_ARB_STRICT_FIFO UVM	3	46	June 5, 2026
Queries on Randomization SystemVerilog constraint-randomization , solve-before	1	40	June 4, 2026
For understanding factory usage UVM UVM , set_type_override , factory , Polymorhphism	6	1626	June 3, 2026
Why Is Scoreboard Kept Separate from Agent in UVM? UVM UVM	2	75	June 3, 2026
Understanding the Real Difference Between uvm_resource_db and uvm_config_db UVM UVM	2	46	June 2, 2026
Router scoreboard implementation SystemVerilog UVM , scoreboard	0	45	May 29, 2026
Why Did UVM Creators Make Separate Classes for uvm_transaction and uvm_sequence_item? UVM UVM	1	51	May 26, 2026
repeat vs for loop control variable SystemVerilog	1	49	May 26, 2026
Confusion About uvm_void in UVM Hierarchy UVM UVM	3	55	May 26, 2026
Use case of uvm_void UVM	1	47	May 26, 2026
Are class object handles passed by reference when used are class method arguments? SystemVerilog SystemVerilog	5	1405	May 26, 2026
Advantage of $future_gclk over $past in FV SystemVerilog Coverage , assertion , System-Verilog , SVA , Formal-Verification , FV	0	32	May 25, 2026
Calculating probability for solve x,y before z SystemVerilog SystemVerilog , constraint-randomization , randomization , solve-before	3	77	May 22, 2026
Unable to use MINGW's G++ to compile C++ code with DPI-C Export. SystemVerilog SystemVerilog , dpi-c , export-DPI-C	2	24	May 18, 2026
Constraint SystemVerilog SystemVerilog	25	6598	May 17, 2026
Asynchronous reset assertion SystemVerilog SystemVerilog , assertion , reset	14	8949	May 13, 2026
Expression bit-length and Associativity SystemVerilog SystemVerilog , LRM-Size-Casting	5	86	May 11, 2026
Creating virtual function to get 'uvm_analysis_export' handles UVM	2	71	May 8, 2026
To check that a signal toggles at least once every 20 cycles SystemVerilog assertion , SVA	11	348	May 6, 2026
Assertion property to check for toggle count of a signal between two control signals SystemVerilog SystemVerilog , assertion , System-Verilog	12	1691	May 6, 2026
P_sequencer and m_sequencer UVM UVM	13	56251	April 28, 2026
Multiple dist constraints SystemVerilog SystemVerilog , constraint-dist , systemverilog-distribution-constraints	5	125	April 27, 2026
Stable pwrite until pready SystemVerilog assertion	4	89	April 24, 2026

Output observation for $dist_exponential

SystemVerilog

SystemVerilog , dist_exponential , Distribution-Function

3

43

June 11, 2026

Why Use convert2string() in UVM When We Can Simply Use display()?

UVM

1

31

June 10, 2026

Use of lock() method

UVM

3

47

June 9, 2026

UVM_SEQ_ARB_WEIGHTED Arbitration: How Does It Work and When Should It Be Used?

UVM

1

51

June 8, 2026

Why does UVM need both wait_for_grant() and wait_for_item_done()?

UVM

3

53

June 8, 2026

UVM Sequencer Arbitration: Is Sequence Priority Used During Queue Insertion or During Grant Selection?

UVM

3

34

June 8, 2026

vmm1.2.2b source tar

Downloads

0

18

June 8, 2026

Understand the Difference between UVM_SEQ_ARB_FIFO and UVM_SEQ_ARB_STRICT_FIFO

UVM

3

46

June 5, 2026

Queries on Randomization

SystemVerilog

constraint-randomization , solve-before

1

40

June 4, 2026

For understanding factory usage

UVM

UVM , set_type_override , factory , Polymorhphism

6

1626

June 3, 2026

Why Is Scoreboard Kept Separate from Agent in UVM?

UVM

2

75

June 3, 2026

Understanding the Real Difference Between uvm_resource_db and uvm_config_db

UVM

2

46

June 2, 2026

Router scoreboard implementation

SystemVerilog

UVM , scoreboard

0

45

May 29, 2026

Why Did UVM Creators Make Separate Classes for uvm_transaction and uvm_sequence_item?

UVM

1

51

May 26, 2026

repeat vs for loop control variable

SystemVerilog

1

49

May 26, 2026

Confusion About uvm_void in UVM Hierarchy

UVM

3

55

May 26, 2026

Use case of uvm_void

UVM

1

47

May 26, 2026

Are class object handles passed by reference when used are class method arguments?

SystemVerilog

5

1405

May 26, 2026

Advantage of $future_gclk over $past in FV

SystemVerilog

Coverage , assertion , System-Verilog , SVA , Formal-Verification , FV

0

32

May 25, 2026

Calculating probability for solve x,y before z

SystemVerilog

SystemVerilog , constraint-randomization , randomization , solve-before

3

77

May 22, 2026

Unable to use MINGW's G++ to compile C++ code with DPI-C Export.

SystemVerilog

SystemVerilog , dpi-c , export-DPI-C

2

24

May 18, 2026

Constraint

SystemVerilog

25

6598

May 17, 2026

Asynchronous reset assertion

SystemVerilog

SystemVerilog , assertion , reset

14

8949

May 13, 2026

Expression bit-length and Associativity

SystemVerilog

SystemVerilog , LRM-Size-Casting

5

86

May 11, 2026

Creating virtual function to get 'uvm_analysis_export' handles

UVM

2

71

May 8, 2026

To check that a signal toggles at least once every 20 cycles

SystemVerilog

assertion , SVA

11

348

May 6, 2026

Assertion property to check for toggle count of a signal between two control signals

SystemVerilog

SystemVerilog , assertion , System-Verilog

12

1691

May 6, 2026

P_sequencer and m_sequencer

UVM

13

56251

April 28, 2026

Multiple dist constraints

SystemVerilog

SystemVerilog , constraint-dist , systemverilog-distribution-constraints

5

125

April 27, 2026

Stable pwrite until pready

SystemVerilog

assertion

4

89

April 24, 2026