Verification Academy

Topic	Replies	Views	Activity
Uvm_scoreboard run_phase wrt queue logic UVM Queues , UVM-scoreboard	3	51	June 2, 2025
Constraining WStrb SystemVerilog constraint-randomization , randomization	2	148	June 1, 2025
Assertion to find the difference between two clocks SystemVerilog Assertion-system-verilog	1	43	June 2, 2025
Bit Precision used during following assignment SystemVerilog	1	24	June 2, 2025
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	23	11660	June 1, 2025
Uvm qvip axis slave tready delay UVM	1	19	May 30, 2025
PCIe Question about LCRC and ECRC! SystemVerilog SystemVerilog , UVM , PCIe , PCIe-Gen-5 , pcie-protocol-explanation	1	37	May 30, 2025
SystemVerilog Assertions Free/Symbolic Variable Usage Error SystemVerilog Formal-Verification , Assertion-system-verilog , free-variable , symbolic-variable	1	53	May 23, 2025
Specifying bit ranges of arrays in VCD SystemVerilog LRM	4	22	May 29, 2025
Liveness and safety property in formal verification SystemVerilog assertion , SVA	1	31	May 29, 2025
Functional Coverage for AXI interconnect Coverage	1	326	May 29, 2025
A better way of getting response back to a waiting sequence? UVM	4	567	May 29, 2025
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	22	11406	May 29, 2025
Scoreboard logic for a router. [Interview Question] UVM UVM-scoreboard	0	51	May 28, 2025
Using sum() to Calculate the Sum of a 2D Array SystemVerilog SystemVerilog , systemverilog-Arrays	11	2241	May 28, 2025
Illegal assignment mailbox error SystemVerilog	4	29	May 28, 2025
Number of semaphore keys. created keys are not matching with get and put SystemVerilog SystemVerilog	4	35	May 28, 2025
Asynchronous input transacation to scoreboard UVM	1	59	December 16, 2024
Constraint Solver error SystemVerilog	5	65	May 27, 2025
First Step in Design Verification UVM UVM , Verification , Formal-Verification , RAL-UVM	2	66	May 27, 2025
Memory Verification without RAL UVM uvm-ral , Debug	1	47	May 27, 2025
Uvm_config_db from bottom to top UVM uvm_config_db	3	45	May 26, 2025
Small typo in the code example of chapter: Testbench Configuration in UVM Cookbook UVM testbench-configuration	0	19	May 25, 2025
IEEE Std 1800™-2023: 7.12.5 Array mapping method SystemVerilog	1	47	May 23, 2025
Number of coverpoint bins SystemVerilog SystemVerilog	3	43	May 23, 2025
Observing duplicate bins within covergroup instance SystemVerilog SystemVerilog , covergroup	3	47	May 22, 2025
Assertion for 55mhz clock SystemVerilog	3	70	May 22, 2025
Counter assertion SystemVerilog SystemVerilog	2	2360	May 22, 2025
VPI printf 4-bit logic type SystemVerilog	1	20	May 22, 2025
Issue with Defining a 2D Non-Deterministic Array in Formal Verification Property SystemVerilog assertion	0	35	May 21, 2025