Verification Academy

Topic	Replies	Views	Activity
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	50	October 15, 2025
SystemVerilog reason of not putting always in program block SystemVerilog SystemVerilog	1	39	October 15, 2025
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	5	35	October 12, 2025
Need clarification on static method and non static method SystemVerilog SystemVerilog , non-static-method , static-method	11	4275	October 12, 2025
Coverpoint for groups of address SystemVerilog Coverage	1	30	October 10, 2025
Getting the virtual interface in the test class or in the agent? UVM	1	35	October 9, 2025
Protected registers behavior implementation with RAL UVM UVM	1	50	October 8, 2025
Query on Register wr/rd verification by taking security state into consideration UVM RAL	2	37	October 8, 2025
Random stability with non-random object SystemVerilog SystemVerilog , questasim , questa , random-stability	2	27	October 8, 2025
Write method as task UVM	6	34	October 8, 2025
Loop to randomize RAL fields across multiple registers SystemVerilog UVM	0	27	October 8, 2025
Updating UVM Component properties via Field Automation Macros UVM apply_config_settings , field-macros , UVM-field-macros , superbuild_phase	7	54	October 8, 2025
Delay in update of mirrored value in explicit prediction UVM RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR	7	46	October 8, 2025
Backdoor Read consumes simulation time UVM RAL , UVM_BACKDOOR , uvm_ral	2	55	October 8, 2025
Why my DPI-C failed after using declaring C function - write()? SystemVerilog export-DPI-C	7	41	October 6, 2025
Trying to cover the following Transition coverage SystemVerilog Coverage , Transition-Coverage	0	29	October 6, 2025
Doubts on cover property & cover sequence SystemVerilog assertion , cover-property , cover-sequence , cover-property-vs-cover-sequen	0	35	October 4, 2025
Driving reset signal correctly SystemVerilog	1	38	October 6, 2025
Blocking statement question SystemVerilog	1	30	October 5, 2025
Cannot pass struct through uvm_config_db UVM uvm-config_db	3	34	October 3, 2025
Assertion for clock gating SystemVerilog SystemVerilog	1	56	October 3, 2025
How to associate callbacks with analysis ports in a layered UVM protocol for error injection UVM	0	18	October 2, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM UVM	6	40	October 2, 2025
Best approach to achieve prime number via constraint SystemVerilog constraint-randomization , randomization , prime-number-constraint	4	94	October 2, 2025
Clarification of "processed" wrt including vs importing for compiler directives SystemVerilog	2	19	October 2, 2025
Can UPF functions be used in uvm sequence class UVM	1	28	September 30, 2025
Dynamic Array- System Verilog SystemVerilog SystemVerilog	1	48	September 30, 2025
Strange $sscanf() behavior in string with two hex values with 0x prefixes SystemVerilog	2	31	September 29, 2025
Is there a way to get around a generate for loop allowing only one genvar variable SystemVerilog	3	35	September 29, 2025
Accessing variables in overridden class UVM	1	27	September 29, 2025

Getting last transaction in consumer repetitively even though producer is sending all transaction

UVM

SystemVerilog , UVM

3

50

October 15, 2025

SystemVerilog reason of not putting always in program block

SystemVerilog

1

39

October 15, 2025

Excluding the already defined bins

Coverage

SystemVerilog , Coverage , Dave-Rich

5

35

October 12, 2025

Need clarification on static method and non static method

SystemVerilog

SystemVerilog , non-static-method , static-method

11

4275

October 12, 2025

Coverpoint for groups of address

SystemVerilog

Coverage

1

30

October 10, 2025

Getting the virtual interface in the test class or in the agent?

UVM

1

35

October 9, 2025

Protected registers behavior implementation with RAL

UVM

1

50

October 8, 2025

Query on Register wr/rd verification by taking security state into consideration

UVM

RAL

2

37

October 8, 2025

Random stability with non-random object

SystemVerilog

SystemVerilog , questasim , questa , random-stability

2

27

October 8, 2025

Write method as task

UVM

6

34

October 8, 2025

Loop to randomize RAL fields across multiple registers

SystemVerilog

UVM

0

27

October 8, 2025

Updating UVM Component properties via Field Automation Macros

UVM

apply_config_settings , field-macros , UVM-field-macros , superbuild_phase

7

54

October 8, 2025

Delay in update of mirrored value in explicit prediction

UVM

RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR

7

46

October 8, 2025

Backdoor Read consumes simulation time

UVM

RAL , UVM_BACKDOOR , uvm_ral

2

55

October 8, 2025

Why my DPI-C failed after using declaring C function - write()?

SystemVerilog

export-DPI-C

7

41

October 6, 2025

Trying to cover the following Transition coverage

SystemVerilog

Coverage , Transition-Coverage

0

29

October 6, 2025

Doubts on cover property & cover sequence

SystemVerilog

assertion , cover-property , cover-sequence , cover-property-vs-cover-sequen

0

35

October 4, 2025

Driving reset signal correctly

SystemVerilog

1

38

October 6, 2025

Blocking statement question

SystemVerilog

1

30

October 5, 2025

Cannot pass struct through uvm_config_db

UVM

uvm-config_db

3

34

October 3, 2025

Assertion for clock gating

SystemVerilog

1

56

October 3, 2025

How to associate callbacks with analysis ports in a layered UVM protocol for error injection

UVM

0

18

October 2, 2025

How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times

UVM

6

40

October 2, 2025

Best approach to achieve prime number via constraint

SystemVerilog

constraint-randomization , randomization , prime-number-constraint

4

94

October 2, 2025

Clarification of "processed" wrt including vs importing for compiler directives

SystemVerilog

2

19

October 2, 2025

Can UPF functions be used in uvm sequence class

UVM

1

28

September 30, 2025

Dynamic Array- System Verilog

SystemVerilog

1

48

September 30, 2025

Strange $sscanf() behavior in string with two hex values with 0x prefixes

SystemVerilog

2

31

September 29, 2025

Is there a way to get around a generate for loop allowing only one genvar variable

SystemVerilog

3

35

September 29, 2025

Accessing variables in overridden class

UVM

1

27

September 29, 2025