Could you please clarify in which region clocking block posedge of clock is executed
|
|
3
|
41
|
May 4, 2024
|
Coverage collector or subscriber usage
|
|
0
|
31
|
May 4, 2024
|
Setting a word-length parameter using $bits on struct field
|
|
1
|
26
|
May 3, 2024
|
Is clocking block driving logic is equivalent to the following?
|
|
1
|
33
|
May 2, 2024
|
Smart way to bundle up multiple RTL signals when passing to monitor
|
|
1
|
33
|
May 2, 2024
|
Overriding a parameter
|
|
9
|
14751
|
May 1, 2024
|
Uvm sequence body does not start after completion of base sequence pre_body
|
|
3
|
37
|
May 1, 2024
|
Uvm_reg_data_t constraint randomization
|
|
2
|
39
|
May 1, 2024
|
SVA - fundamental questions
|
|
5
|
39
|
May 1, 2024
|
Randc variable randomization inside top sequence class
|
|
3
|
38
|
May 1, 2024
|
Analysis Port Write functionality
|
|
1
|
27
|
April 30, 2024
|
Web Seminar - Beyond UVM: Effectively Modeling and Analyzing Coverage
|
|
0
|
3544
|
November 21, 2012
|
Introducing the Coverage Cookbook
|
|
1
|
4089
|
March 19, 2013
|
UVM/OVM Recipe of the Month - Intro to UVM Registers
|
|
0
|
5682
|
October 4, 2011
|
Have you heard? There's a new Academy course, Introduction to the UVM
|
|
0
|
1759
|
August 6, 2014
|
How to cover unsigned int
|
|
1
|
50
|
April 30, 2024
|
Web Seminar Notification: New School Thinking for Fast and Efficient Verification Using EZ-VIP
|
|
0
|
1581
|
April 20, 2015
|
Web Seminar Notification: New School Coverage Closure
|
|
0
|
1553
|
May 20, 2015
|
SystemVerilog Hiearchial Reference to UUT Internal Signal?
|
|
2
|
32
|
April 30, 2024
|
System verilog inheritance for sequences
|
|
4
|
39
|
April 30, 2024
|
Want to generate array of one hot numbers using system Verilog constraints
|
|
2
|
47
|
April 30, 2024
|
How to give variable delay based on signal in SV assertion
|
|
1
|
44
|
April 29, 2024
|
Ahb protocol during first transfer when hready is low what happens
|
|
1
|
30
|
April 28, 2024
|
Using sequence method triggered within Sampled value functions
|
|
5
|
83
|
April 27, 2024
|
How can you set order for the execution of initial begin blocks without using event or wait statements?
|
|
1
|
32
|
April 27, 2024
|
How text macro affect inside and outside pkg?
|
|
2
|
30
|
April 27, 2024
|
Example of Constructors from LRM
|
|
3
|
38
|
April 26, 2024
|
How do you compare negative integers in systemVerilog?
|
|
5
|
51
|
April 26, 2024
|
How to know about which seed is running and getting randomize when my seed is processed randomly?
|
|
5
|
381
|
April 26, 2024
|
Clarifications about uvm_config db performance
|
|
3
|
63
|
April 26, 2024
|