Verification Academy

Topic	Replies	Views	Activity
Interface and Virtual interface SystemVerilog Interfaces	1	31	November 29, 2024
Generate the sequence using constraint SystemVerilog SystemVerilog , constraint-randomization , systemverilog-uvm , systemverilog-constraint	2	217	November 29, 2024
Why Override the Default Sequence for Reactive Slaves in UVM? UVM UVM	4	35	November 28, 2024
Assertion for a signal until a sequence is triggered SystemVerilog assertion	6	49	November 27, 2024
Error-[ICTTFC] Incompatible complex type usage UVM	1	16	November 27, 2024
Printing detailed UVM testbench toplogy UVM SystemVerilog	1	41	November 27, 2024
SV Constraint with Permutations and Combinations SystemVerilog	4	72	November 25, 2024
Cover property/sequence for transaction objects SystemVerilog SystemVerilog , Coverage , property	0	22	November 26, 2024
RAL Coverage , Multiple Instance issue UVM RAL	2	28	November 26, 2024
Clock Inference for Embedded concurrent assertion SystemVerilog SystemVerilog , assertion , SVA , embedded-concurrent-assertion	2	46	November 25, 2024
How can a task return a Queue? SystemVerilog SystemVerilog , task , return-data , functions-in-system-verilog	9	7818	November 26, 2024
Difference between using configuration space vs configuration object UVM	3	26	November 25, 2024
Bit Constraints of each element in array SystemVerilog constraints	6	71	November 25, 2024
Constraint Randomization Interview Question SystemVerilog SystemVerilog	21	4863	November 25, 2024
Write a constraint to generate the pattern 1234554321 SystemVerilog SystemVerilog , systemverilog-constraint	3	75	November 25, 2024
Embedding concurrent assertions in procedural code SystemVerilog SystemVerilog , assertion , SVA	2	316	November 25, 2024
UVMC 2.3.3 is compatible with uvm-ieee-2020 or not UVM UVMC-Compilation	0	18	November 25, 2024
Requirement to initialize dynamic variables within property/sequence SystemVerilog assertion , System-Verilog , SVA	3	378	November 25, 2024
Lock in virtual sequence UVM	4	36	November 25, 2024
Regarding UVM_QUEUE and their methods UVM OVM , SystemVerilog , UVM	2	48	November 25, 2024
Question on Sequence concatenation '##' SystemVerilog SystemVerilog , assertion , SVA	1	30	November 24, 2024
2D array constraint randomization SystemVerilog SystemVerilog , 2D-array-SystemVerilog-randomization	18	5685	November 24, 2024
Legal declaration of concurrent assertion statement SystemVerilog SystemVerilog , assertion , SVA , concurrent-assertion	2	27	November 23, 2024
Driver will ask to sequence to do randomization in uvm UVM UVM	1	35	November 22, 2024
Write constraint for an integer array with 10 elements such that exactly 3 of them are same and rest are unique SystemVerilog SystemVerilog , unique-array	9	2156	November 20, 2024
Toggle Coverage for a 8bit variable UVM functional-coverage	1	48	November 20, 2024
How using Functional Coverage we can find out, if there is any missing functionality in the DUT? SystemVerilog SystemVerilog	4	852	November 20, 2024
Factory in RAL , create vs new UVM RAL	1	41	November 19, 2024
Mirrored value in frontdoor and backdoor UVM RAL	1	32	November 19, 2024
Constraining OCM base addresses SystemVerilog SystemVerilog , constraint-randomization	1	39	November 19, 2024