SVA - fundamental questions

I had some fundamental questions on SVA:

  1. In a typical UVM env, where all my reference data is only available in the the scoreboard, how can I make reference data available while writing assertions? I cannot have concurrent assertions inside UVM scoreboard or inside any class. Yet, I see examples on the forum where after certain conditions are met, in the same assertion, DUT data is compared to reference data.
    For example here: Assertion: Expected data check // A review from a user's question

  2. Where do DV folks write concurrent assertions typically in a UVM DV environment? Interface module?

Highly appreciate your inputs! Thanks.

See my paper

Also, checkout my other papers.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

Thanks Ben.

Follow up question:
In this paper: SVA in a UVM Class-based Environment.

Its said `

logic [15:0] expected_data; // <– supplied by

                scoreboard`

How do I get the expected data from scoreboard to interface? Through config_db/uvm_resource_db ? (probably not). Then, how?

Thanks again for your guidance.

A class can connect to one or more interfaces. You could dedicate one ifc for the DUT and another one for the assertions, but for simplicity,you can also have just one ifc. In any case, the class needs to copy the class variables into the ifc.
If the class variables are static, I believe that those static class variables can be directly accessed by the ifc with something like class_name.var_name. The class variables are modified by the class tasks.
Am I missing something here?

Thank you, Ben.

Do you happen to have example code on how a scoreboard (that extends uvm_scoreboard) can talk to interface definition where I have my assertions coded?

Thank you again for your help as I try to connect the dots…

The concepts are very simple and are demonstrated in
https://systemverilog.us/verizons/sc2uvm.sv
From the previously mentioned paper, I explain in
Minimizing use of scoreboarding with assertions
Since the concurrent assertions cannot execute in classes, but in modules and interfaces, we use interfaces tomwrite the assertions.
The SVA properties in the interface (ifc) can directly access static class variables and interface signals. Thus, you could use a
task in the class to copy the values of non-static class variables into a SystemVerilog interface (or into static class variables). The assertions in the interface makes use of the copied variables (or directly static class variables) and other signals of the interface to determine compliance to the requirements. Where you do those copies is dependent upon the problem at hand. The driver may know the expected response.
Maybe a computation is needed here. A scoreboard may know what the response should be. For example, if you write to a memory, and associative array (stored in a class or in the ifc can store that write value).