Example of Constructors from LRM

SystemVerilog
1

I don’t understand the following example from the LRM under the “Constructors” section (8.7).

Here is the code:

class C;
  int c1 = 1;
  int c2 = 1;
  int c3 = 1;
  function new(int a);
    c2 = 2;
    c3 = a;
  endfunction
endclass
class D extends C;
  int d1 = 4;
  int d2 = c2;
  int d3 = 6;
  function new;
    super.new(d3);
  endfunction
endclass

When calling the constructor of class D, I thought c3 should be 6 But the LRM says that it should be undefined. Why is that? I didn’t get the explanation in the LRM.

2

All class constructors are for the most part executed as:

function new;
   <implicit or explicit call to super.new>
   <variable initializations>
   <body of constructor>
endfunction

Effectively the base constructor is called first followed by the extended extended constructor. This allows memory allocation for the class to follow construction of the base to extended class. SystemVerilog leaves its value undefined because either initialization has not happened yet, and/or memory has not be allocated for the variable yet.

1 Like
3

But for the example provided, doesn’t the line

int d3 = 6;

initialize the variable d3 to 6? Therefore, shouldn’t the value passed into the base constructor be 6?

4

No. The initialization does not happen until after returning from super.new.