I am pretty new to verification and trying to figure something out, but the overall architecture of the testebcnh is a bit confusing to me. I want to display or check the value of some internal signal of my UUT, but I am not sure how to access it from the testbench. Input and output ports can easily be accessed through the interface but the signal I want to read is not an input/output. I am trying to do a hierarchical name reference but obviously, what I am doing is not correct. I am trying to access a signal inside my testcase by doing something like
UUT_top_inst.module_name.signal_name
The testcases exist inside a class, that is inside a package that is imported into the testbench module. I have attempted to show this architecture in this block diagram, but there may be some mistakes here. Can anyone provide me with some guidance on how I can do this?
