Smart way to bundle up multiple RTL signals when passing to monitor

SystemVerilog
,
1

Hi I am trying to clean up legacy code in SV. The way signals are hookup between monitor and RTL is through bind

bind rtl_top a_monitor a_monitor_u(
  .abc ({`PATH_TO_MODULE0.sig1,
`PATH_TO_MODULE1.sig2,
`PATH_TO_MODULE2.sig3,
`PATH_TO_MODULE3.sig4,
`PATH_TO_MODULE4.sig5
})
);

in monitor abc is defined as an array
bit abc [5];

Is there a cleaner way to handle RTL signal declaration? If in next project MODULE increases to 20, have to manually add lines of code.

There is no interface defined, so cant use interface to pass signals

2

Unless there is an index n as part of `PATH_TO_MODULE[n].sig[n+1], there is no cleaner way.