How do you compare negative integers in systemVerilog?

SystemVerilog
1

Here is a very simple dummy function, where I am trying to check is -1 is less than -2. -2 should be a smaller number, but does not seem that is whats happening in this function. Can someone explain to be what is going on here?

module tb;
  
  function dummy_function();
    
    begin
      int temp = -1;
      
      if(temp < -2) begin
        $display("Temp (%0d) is smaller than -2", temp);
      end else begin
        $display("Temp (%0d) is larger than or equal to -2", temp);
      end
    end
  endfunction

  initial begin
    dummy_function();
  end
  
endmodule
2

Iā€™m not sure what you think is a problem. The expression (-1 < -2) should be false because -1 is greater than -2.

3

I agree, but the console output is still printing this:

image
image1270Ɨ745 30.2 KB

4

If I do the following, it works as expected. It seems like the -2 is not treated as a signed number unless its explicitly stored in an int? I dont quite understand whats happening here

module tb;
  
  function dummy_function();
    
    begin
      int temp = -1;
      int max = -2;
      
      if(temp < max) begin
        $display("Temp (%0d) is smaller than (%d)", temp, -2);
      end else begin
        $display("Temp (%0d) is larger than or equal to -2", temp);
      end
    end
  endfunction

  initial begin
    dummy_function();
  end
  
endmodule
1 Like
5

You have run into a tool bug. iverilog support of SystemVerilog is not very good. If you change the declaration of temp to integer, you get the correct result.

6

Okay, thank you for the tip!