How to cover unsigned int

UVM
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1

Hello everyone, thank you very much for your help.

I want to cover a 32-bit count register。
I write it like this：

covergroup tran_octets_count_reg_cov with function sample( bit [31:0] count); 
    option.name = "octets_count_reg_cov";
    option.per_instance = 1;

    TRAN_OCTETS : coverpoint count{
        bins tx_oct_1[ ] = {[0:2147483646]};
        bins tx_oct_2[ ] = {[2147483647:4294967290]};
        bins tx_oct_3[ ] = {[4294967291:4294967295]};
    }
endgroup

But it gives a warning that count is considered a signed number

Parsing included file '../env/mac_reg_cov_mon.svh'.

Warning-[DCTL] Decimal constant too large
../env/mac_reg_cov_mon.svh, 89
  Decimal constant '4294967290' is too large as a 32bit signed constant, it 
  should be smaller than 2147483648.
  VCS is using converted signed value '-6' instead.
  To make it an unsigned constant, please use sized constant format.

Here are some of my attempts, but it still doesn’t work.
(1) I’ve avoided passing in other types of values, and even if I write a covergroup
that isn’t called, it will warn.Is this not a good way to write constraints ?
(2) I tried to replace bit [31:0] with longint to widen the range, but it still got a
warning

Can someone help me?
Best wishes !

2

You are not reading the error message correctly. The problem is with the decimal constant 4294967290 and larger. Decimal constants have an integer datatype, and that constant is too large as an integer. You can write 'd4294967290 instead which is treated as unsigned.