address phase is only one cycle right.in first cycle i get address and control signals and hready is zero.then after 3 clock cycle hready is high and data transfer is accepted by slave .so what happens between 1 cycle and 2 cycle and 3 cycle
I am not sure if the following answers your specific question, but I used the AHB protocol as a specification model tomwrite PSL assertions for my PSL book. The assertions and my discussion and code on AHB may help you understand the protocol.
Assertion example from my PSL book.
Although I do not recommend PSL, I am contributing a chapter from my PSL book (before SVA) that demonstrates how assertions can be used to clarify requirements and verification processes. This chapter showcases a design that includes an AMBA™ AHB bus and an IDT 71V433 Synchronous pipelined SRAM2.
The chapter (and code) also includes simulation results of the model using a PSL-aware simulator for verification.
My goal here is to demonstrate assertion approaches and their values in the clarification of the requirements, design and verification processes. Though written in PSL, the assertions can easily be converted into SVA; SVA was derived from PSL.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
http://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf