How to give variable delay based on signal in SV assertion

SystemVerilog
1

I want to create an assertion based on variable delay from a signal.
Example is I have signal delay and need to create an assertion like below.

a ##[0:delay] b;

How to achieve this variable delay in delay range assertions ?

1 Like
2

Use my SVAPackage: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy Provides a library and model solutions
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf