UVM: Registers/Configuration
During verification a programmable hardware device needs to be configured to operate in different modes. The register model can be used to automate or to semi-automate this process.
The register model contains a shadow of the register state space for the DUT which is kept up to date as the design is configured using bus read and write cycles. One way to configure the design in a testbench is to apply reset to the design and then go through a programming sequence which initializes the design for a particular mode of operation.
