Q: Who should be using UVM Connect?
A: Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment. It also includes SystemVerilog designers who want to use SystemC models as reference models in their environment or any other application that requires components of both languages to run together.
Q: Is UVM Connect a package separate from UVM?
A: Yes, UVM Connect is a separate package that is loaded independently from your UVM and/or SystemC environment. The UVM Connect kit includes the library code, examples and a hypertext User's Guide.
Q: How do I connect a UVM SystemVerilog component to a SystemC component?
A: Both UVM and SystemC support the TLM1 and TLM 2 interface standards. UVM Connect lets you connect TLM ports in one language to the corresponding TLM ports in the other. The library allows you to specify converter functions to transform the transaction object between languages. If you are already using the TLM generic payload, the conversion is handled automatically.
Q: How does SystemC control or interact with UVM SystemVerilog?
A: UVM Connect defines an API that allow SystemC models to affect UVM behaviors, including set/get config, factory overrides and issuing UVM messages.
Q: Do I need to rewrite my SystemC environment or components to mimic UVM structures or functionality?
A: No. Since SystemC already supports TLM, your existing SystemC components and environment can be used as-is with UVM Connect.
Q: UVMC-2.2 had a limitation on data payload sizes for TLM generic payloads. Is there a way around this?
A: UVMC-2.3 offers a special type of packer called a "fast packer" that can be used with UVM-Connections by specifying the new converter data types with the 'uvmc_connect()" calls. These remove any limitations on the size of the data payloads.
