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  • UVM Connect

UVM Connect

UVM Connect

UVM Connect is an open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). UVM Connect allows you to reuse your SystemC architectural models as reference models in UVM verification and/or reuse SystemVerilog UVM agents to verify models in SystemC. It also effectively expands your VIP portfolio since you now have access to VIP in both languages. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.

Version 2.3 of UVM adds new "fast packers" capability for improved performance when passing generic payloads across TLM2 connections. They also add support for unlimited data payloads and limited support for configuration extensions.

   UVM - Universal Verification Methodology

UVM Connect Sessions

Introduction to UVM Connect

This session introduces UVM Connect and explains the benefits of adoption.

Connections

This session shows how to establish connections between components.

Converters

This session shows how to write the converters that are needed to transfer transaction data.

UVM Command API

This session shows how control key aspects of UVM simulation from SystemC.

UVM Connect Resources

  • Downloads
  • FAQ
  • Course
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  • Web Seminar

UVM Connect 2.3.1

The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.

  • 2.3.1 Kit
  • 2.3.1 HTML Reference
  • HTML Tarball
  • View Primer

UVM Connect 2.3.0

The UVM Connect library makes connecting TLM models in SystemC and UVM in SystemVerilog a relatively straightforward process. Download the complete working example:

  • 2.3.0 Kit
  • 2.3.0 HTML Reference
  • View Primer

UVM Connect 2.2

This download includes the complete UVM Connect 2.2 Kit from the Methodology Cookbook:

  • 2.2 Kit
  • 2.2 Guide

Q: Who should be using UVM Connect?

A: Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment. It also includes SystemVerilog designers who want to use SystemC models as reference models in their environment or any other application that requires components of both languages to run together.

Q: Is UVM Connect a package separate from UVM?

A: Yes, UVM Connect is a separate package that is loaded independently from your UVM and/or SystemC environment. The UVM Connect kit includes the library code, examples and a hypertext User's Guide.

Q: How do I connect a UVM SystemVerilog component to a SystemC component?

A: Both UVM and SystemC support the TLM1 and TLM 2 interface standards. UVM Connect lets you connect TLM ports in one language to the corresponding TLM ports in the other. The library allows you to specify converter functions to transform the transaction object between languages. If you are already using the TLM generic payload, the conversion is handled automatically.

Q: How does SystemC control or interact with UVM SystemVerilog?

A: UVM Connect defines an API that allow SystemC models to affect UVM behaviors, including set/get config, factory overrides and issuing UVM messages.

Q: Do I need to rewrite my SystemC environment or components to mimic UVM structures or functionality?

A: No. Since SystemC already supports TLM, your existing SystemC components and environment can be used as-is with UVM Connect.

Q: UVMC-2.2 had a limitation on data payload sizes for TLM generic payloads. Is there a way around this?

A: UVMC-2.3 offers a special type of packer called a "fast packer" that can be used with UVM-Connections by specifying the new converter data types with the 'uvmc_connect()" calls. These remove any limitations on the size of the data payloads.

UVM Connect

UVM Connect Course | Subject Matter Expert - Adam Erickson | UVM/OVM Topic

UVM Connect will demonstrate how to reuse your SystemC architectural models and/or reuse SystemVerilog UVM agents to verify models in SystemC.

UVM Connect

So what does this new capability allow you to do? UVM Connect enables the following use models, all designed to maximize IP reuse: Abstraction Refinement— Reuse your SystemC architectural models as reference models in UVM verification.
Horizons Article

UVM Connect Interview

Graham Bell from EDA Cafe interviews Tom Fitzpatrick at DVCon 2012.
Watch Interview

OVM Gets Connected

When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages.
Blog Post

Mentor Graphics Extends UVM Connect to Support OVM

The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With UVM Connect 2.2, teams using OVM can connect with SystemC models and other environments as well.
Press Release

Introducing UVM Connect

As design teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models becomes imperative. Design and verification teams work with a plethora of functional models sourced in different design languages, primarily SystemC and SystemVerilog, where the choice of language is made in order to exploit the advantages of the native language.
Blog Post

Mentor Graphics Drives Broader Adoption of UVM

As design teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models becomes imperative. Design and verification teams work with a plethora of functional models sourced in different design languages, primarily SystemC and SystemVerilog, where the choice of language is made in order to exploit the advantages of the native language.
Press Release

UVM Connect Overview

UVM Connect provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).
Cookbook Recipe

UVM Connect Connections

To communicate, verification components must agree on the data they are exchanging and the interface used to exchange that data. TLM connections parameterized to the type of object (transaction) help components meet these requirements and thus ease integration costs and increase their reuse.
Cookbook Recipe

UVM Connect Conversion

UVMC provides built-in support for the TLM generic payload (TLM GP). You don't need to do anything regarding transaction conversion when using TLM GP. Use of the TLM GP also affords the best opportunity for interoperability between independently designed components from multiple IP suppliers
Cookbook Recipe

UVM Connect Command API

Use of configuration objects is strongly recommended over one-at-a-time integrals and strings. You can pass configuration for an entire component or set of components with a single call, and the configuration object is type-safe to the components that accept those objects.
Cookbook Recipe

UVM Connect

UVM Connect Session | Subject Matter Expert - Tom Fitzpatrick | UVM Recipe of the Month Seminar

This Verification Cookbook seminar introduces UVM Connect; providing TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components.

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