Error in uvm_config_db

UVM
,
1

I want to create a generic part of uvm_config_db for 2 interfaces, slave and master for that i have :

tb.sv : first module which has specific interface and must be included in my top_tb.sv (top_level)
but when i try to do this i have this error :
(vlog-2730) Undefined variable: ‘slave_interface’****.
(vlog-2730) Undefined variable: ‘master_interface’****.

this the part of code for this both :

for tb.sv (part of uvm_config_db)__

initial begin 
      uvm_config_db#(virtual apb_interface)::set(null, "*", "slave_interface", apb_s0);
      uvm_config_db#(virtual ahb_interface)::set(null, "*", "master_interface", ahb_m0);
end

for top_tb.sv __

`include "tb.sv" 
module top_tb; 
  initial begin 
    $timeformat ( -6, 3, " us", 10);

    uvm_config_db#(type(slave_interface))::get(null, "", "slave_interface", slave_interface);
    uvm_config_db#(type(master_interface))::get(null, "", "master_interface", master_interface);

    uvm_config_db#(type(slave_interface))::set(null, "uvm_test_top.env.slave_agent*", "vif", slave_interface);
    uvm_config_db#(type(master_interface))::set(null, "uvm_test_top.env.master_agent*", "vif", master_interface);
    
    run_test() ;
  end     
endmodule  : top_tb

Thanks,

2

In reply to uvm_share:

A few remarks:
(1) in tb.sv we do not see the instances apb_s0 and apb_m0.Do they exist?
(2) your slave_interface is the sam interface as the master interface. This results from the setings in tb.sv
(3) in top_tb your settings are wrong. The first 2 uvm_config_db shoule be like this:

uvm_config_db#(virtual apb_interface)::get(null, "", "slave_interface", slave_interface);
    uvm_config_db#(virtual apb_interface)::get(null, "", "master_interface", master_interface);

(4) in top_tb you need also instances for the master and slave interface, respectively.
(5) What is the objective of the uvm_congig_db set commands in top_tb?

It is a little bit confusing what you are coding.
Please explain in some more detail what your objective is.

3

Thank you for your answer so, my objectif is to make generic uvm_config_db , for this i instaciate it by master and slave interface.

  1. i have the instance of apb_s0 and ahb_m0 in my tb.sv

2 ) i have apb as slave interface and ahb as master interface

  1. i tried it but i have the same error

  2. when i instanciate my master_interface and slave_interface i didn’t resolve the error

5 ) as I had a bridge-specific config_db in tb.sv, and I want to make a generic part in top_tb.sv

4

In reply to uvm_share:

Oh I have overseen the ahb and apb interface.
But you need the interface declared when putting the interface through the config_db.

5

In reply to chr_sue:
Yes, thats what i did, i intanciated like this in tb.sv:

apb_interface slave_interface ; 
ahb_interface master_interface ;
6

In reply to uvm_share:

This declaration requires brackets like this

apb_interface slave_interface(); 
ahb_interface master_interface();
7

In reply to uvm_share:

So much missing code… Here is a complete working example.

interface apb_interface;
  logic clk;
endinterface // apb


interface ahb_interface;
  logic clk;
endinterface // ahb


module tb;
  import uvm_pkg::*;
  apb_interface apb_s0();
  ahb_interface ahb_m0();

  initial begin 
    // ** Use scope of (null,"") to match the get() call
    uvm_config_db#(virtual apb_interface)::set(null, "", "slave_interface", apb_s0);
    uvm_config_db#(virtual ahb_interface)::set(null, "", "master_interface", ahb_m0);
  end
endmodule // tb


module top_tb;
  import uvm_pkg::*;
`include "uvm_macros.svh"

  virtual apb_interface slave_interface;
  virtual ahb_interface master_interface;
  
  initial begin 
    $timeformat ( -6, 3, " us", 10);
    
    uvm_config_db#(type(slave_interface))::get(null, "", "slave_interface", slave_interface);
    uvm_config_db#(type(master_interface))::get(null, "", "master_interface", master_interface);
    
    uvm_config_db#(type(slave_interface))::set(null, "uvm_test_top.env.slave_agent*", "vif", slave_interface);
    uvm_config_db#(type(master_interface))::set(null, "uvm_test_top.env.master_agent*", "vif", master_interface);
    
    run_test("no_test") ;
  end     

class no_test extends uvm_test;
  `uvm_component_utils(no_test)
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  task run_phase (uvm_phase phase );
    `uvm_info("HELLO", "WORLD", UVM_MEDIUM)
  endtask
endclass
endmodule
8

Yes, thank you for your all answers.

So when i try this code :

module top_tb;
  import uvm_pkg::*;
`include "uvm_macros.svh"
 
  virtual apb_interface slave_interface;
  virtual ahb_interface master_interface;
 
  initial begin 
    $timeformat ( -6, 3, " us", 10);
 
    uvm_config_db#(type(slave_interface))::get(null, "", "slave_interface", slave_interface);
    uvm_config_db#(type(master_interface))::get(null, "", "master_interface", master_interface);
 
    uvm_config_db#(type(slave_interface))::set(null, "uvm_test_top.env.slave_agent*", "vif", slave_interface);
    uvm_config_db#(type(master_interface))::set(null, "uvm_test_top.env.master_agent*", "vif", master_interface);
 
    run_test("no_test") ;
  end

I have a error when i want to simulate like it doesn’t find the port to connect interface ahb and apb

9

In reply to uvm_share:
Which simulator you are using?
The code works with VCS and Questa and fails with Xcelium and Riviera. Both simulators cannot deal with

type(master_interface)

And I do not see what the benefit is of using

type(master_interface)

instad of

virtual ahb_interface
10

Thanks for your interaction,

my final objective is to develop unified verif env , for this i need to have a stable part of uvmconfig_db which muste be generic for each interface master and slave. that’s the reason why i declared both types : master and slave

For my simulator, I’m using Questa

11

In reply to uvm_share:

But you cannot reach it. You have to declare the master/slave interfaces explicitely in your top_tb.
See here:

module top_tb;
  import uvm_pkg::*;
`include "uvm_macros.svh"
 
  virtual apb_interface slave_interface;
  virtual ahb_interface master_interface;

And this is my example on Edaplayground:

1 Like
12

Thank you Sir, it is solved Now